DCache: Clear out a rw_wait reference in a $display that caused Verilator to throw...
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
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1`include "ARM_Constants.v"
2
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3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
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21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
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25 input flush,
26
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27 /* bus interface */
28 output reg [31:0] busaddr,
29 output reg rd_req,
30 output reg wr_req,
31 input rw_wait,
32 output reg [31:0] wr_data,
33 input [31:0] rd_data,
9fc6c23c 34 output reg [2:0] data_size,
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35
36 /* regfile interface */
37 output reg [3:0] st_read,
38 input [31:0] st_data,
a02ca509 39
979f2bd7
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40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
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45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
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48 /* stage inputs */
49 input inbubble,
50 input [31:0] pc,
51 input [31:0] insn,
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52 input [31:0] op0,
53 input [31:0] op1,
6d0f9d82 54 input [31:0] op2,
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55 input [31:0] spsr,
56 input [31:0] cpsr,
fdecc897 57 input cpsrup,
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58 input write_reg,
59 input [3:0] write_num,
60 input [31:0] write_data,
b3bb2fb8 61
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62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
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66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897
JW
71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
804dc0bc
JW
81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
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87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
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90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
9a0d0e43
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98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
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100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
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103
104 always @(posedge clk)
105 begin
106 outpc <= pc;
107 outinsn <= insn;
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108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
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112 if (!rw_wait)
113 prev_offset <= offset;
b114e03f 114 prev_raddr <= raddr;
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115 outcpsr <= next_outcpsr;
116 outspsr <= spsr;
fdecc897 117 outcpsrup <= next_outcpsrup;
9a0d0e43 118 swp_state <= next_swp_state;
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119 lsm_state <= next_lsm_state;
120 lsr_state <= next_lsr_state;
121 lsrh_state <= next_lsrh_state;
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122 if (do_rd_data_latch)
123 rd_data_latch <= rd_data;
55c6199c 124 swp_oldval <= next_swp_oldval;
666ceb03 125 prevaddr <= addr;
a02ca509 126 end
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127
128 reg delayedflush = 0;
129 always @(posedge clk)
130 if (flush && outstall /* halp! I can't do it now, maybe later? */)
131 delayedflush <= 1;
132 else if (!outstall /* anything has been handled this time around */)
133 delayedflush <= 0;
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134
135 /* Drive the state machines and stall. */
136 always @(*)
137 begin
138 outstall = 1'b0;
139 next_lsm_state = lsm_state;
140 next_lsr_state = lsr_state;
141 next_lsrh_state = lsrh_state;
142 next_swp_state = swp_state;
143 casez(insn)
144 `DECODE_ALU_SWP: if(!inbubble) begin
145 case(swp_state)
146 `SWP_READING: begin
147 outstall = 1'b1;
148 if (!rw_wait)
149 next_swp_state = `SWP_WRITING;
150 $display("SWP: read stage");
151 end
152 `SWP_WRITING: begin
153 outstall = rw_wait;
154 if(!rw_wait)
155 next_swp_state = `SWP_READING;
156 $display("SWP: write stage");
157 end
158 default: begin
159 outstall = 1'bx;
160 next_swp_state = 2'bxx;
161 end
162 endcase
163 end
164 `DECODE_ALU_MULT: begin end
165 `DECODE_ALU_HDATA_REG,
166 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
167 case(lsrh_state)
168 `LSRH_MEMIO: begin
169 outstall = rw_wait;
170 if(insn[21] | !insn[24]) begin
171 outstall = 1'b1;
172 if(!rw_wait)
173 next_lsrh_state = `LSRH_BASEWB;
174 end
175
176 if (flush) /* special case! */ begin
177 outstall = 1'b0;
178 next_lsrh_state = `LSRH_MEMIO;
179 end
180
181 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
182 end
183 `LSRH_BASEWB: begin
184 outstall = 1'b1;
185 next_lsrh_state = `LSRH_WBFLUSH;
186 end
187 `LSRH_WBFLUSH: begin
188 outstall = 1'b0;
189 next_lsrh_state = `LSRH_MEMIO;
190 end
191 default: begin
192 outstall = 1'bx;
193 next_lsrh_state = 3'bxxx;
194 end
195 endcase
196 end
197 `DECODE_LDRSTR_UNDEFINED: begin end
198 `DECODE_LDRSTR: if(!inbubble) begin
199 outstall = rw_wait;
200 case(lsr_state)
201 `LSR_MEMIO: begin
202 outstall = rw_wait;
203 next_lsr_state = `LSR_MEMIO;
204 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
205 outstall = 1'b1;
206 if (!rw_wait)
207 next_lsr_state = `LSR_STRB_WR;
208 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
209 outstall = 1'b1;
210 if (!rw_wait)
211 next_lsr_state = `LSR_BASEWB;
212 end
213
214 if (flush) begin
215 outstall = 1'b0;
216 next_lsr_state = `LSR_MEMIO;
217 end
218 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
219 end
220 `LSR_STRB_WR: begin
221 outstall = 1;
222 if(insn[21] /* W */ | !insn[24] /* P */) begin
223 if(!rw_wait)
224 next_lsr_state = `LSR_BASEWB;
225 end else if (!rw_wait)
226 next_lsr_state = `LSR_WBFLUSH;
227 $display("LDRSTR: Handling STRB");
228 end
229 `LSR_BASEWB: begin
230 outstall = 1;
231 next_lsr_state = `LSR_WBFLUSH;
232 end
233 `LSR_WBFLUSH: begin
234 outstall = 0;
235 next_lsr_state = `LSR_MEMIO;
236 end
237 default: begin
238 outstall = 1'bx;
239 next_lsr_state = 4'bxxxx;
240 end
241 endcase
242 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
243 end
244 `DECODE_LDMSTM: if(!inbubble) begin
245 outstall = rw_wait;
246 case(lsm_state)
247 `LSM_SETUP: begin
248 outstall = 1'b1;
249 next_lsm_state = `LSM_MEMIO;
250 if (flush) begin
251 outstall = 1'b0;
252 next_lsm_state = `LSM_SETUP;
253 end
254 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
255 end
256 `LSM_MEMIO: begin
257 outstall = 1'b1;
fa42d706 258 if(next_regs == 16'b0 && !rw_wait) begin
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259 next_lsm_state = `LSM_BASEWB;
260 end
261
e92804b3 262 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, st_data, busaddr);
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263 end
264 `LSM_BASEWB: begin
265 outstall = 1;
266 next_lsm_state = `LSM_WBFLUSH;
267 $display("LDMSTM: Stage 3: Writing back");
268 end
269 `LSM_WBFLUSH: begin
270 outstall = 0;
271 next_lsm_state = `LSM_SETUP;
272 end
273 default: begin
274 outstall = 1'bx;
275 next_lsm_state = 4'bxxxx;
276 end
277 endcase
278 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
279 end
280 `DECODE_LDCSTC: if(!inbubble) begin
281 $display("WARNING: Unimplemented LDCSTC");
282 end
283 `DECODE_CDP: if (!inbubble) begin
284 if (cp_busy) begin
285 outstall = 1;
286 end
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287 if (!cp_ack) begin
288 /* XXX undefined instruction trap */
289 $display("WARNING: Possible CDP undefined instruction");
290 end
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291 end
292 `DECODE_MRCMCR: if (!inbubble) begin
293 if (cp_busy) begin
294 outstall = 1;
295 end
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296 if (!cp_ack) begin
297 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
298 end
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299 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
300 end
301 default: begin end
302 endcase
303 end
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304
305 /* Coprocessor input. */
306 always @(*)
307 begin
308 cp_req = 0;
309 cp_rnw = 1'bx;
310 cp_write = 32'hxxxxxxxx;
311 casez (insn)
312 `DECODE_CDP: if(!inbubble) begin
313 cp_req = 1;
314 end
315 `DECODE_MRCMCR: if(!inbubble) begin
316 cp_req = 1;
317 cp_rnw = insn[20] /* L */;
318 if (insn[20] == 0 /* store to coprocessor */)
319 cp_write = op0;
320 end
321 endcase
322 end
323
324 /* Register output logic. */
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325 always @(*)
326 begin
327 next_write_reg = write_reg;
328 next_write_num = write_num;
329 next_write_data = write_data;
330 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
331 next_outcpsrup = cpsrup;
332
333 casez(insn)
334 `DECODE_ALU_SWP: if (!inbubble) begin
335 next_write_reg = 1'bx;
336 next_write_num = 4'bxxxx;
337 next_write_data = 32'hxxxxxxxx;
338 case(swp_state)
339 `SWP_READING:
340 next_write_reg = 1'b0;
341 `SWP_WRITING: begin
342 next_write_reg = 1'b1;
343 next_write_num = insn[15:12];
344 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
345 end
346 default: begin end
347 endcase
348 end
349 `DECODE_ALU_MULT: begin end
350 `DECODE_ALU_HDATA_REG,
351 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
352 next_write_reg = 1'bx;
353 next_write_num = 4'bxxxx;
354 next_write_data = 32'hxxxxxxxx;
355 case(lsrh_state)
356 `LSRH_MEMIO: begin
357 next_write_num = insn[15:12];
358 next_write_data = lsrh_rddata;
359 if(insn[20]) begin
360 next_write_reg = 1'b1;
361 end
362 end
363 `LSRH_BASEWB: begin
364 next_write_reg = 1'b1;
365 next_write_num = insn[19:16];
366 next_write_data = addr;
367 end
368 `LSRH_WBFLUSH:
369 next_write_reg = 1'b0;
370 default: begin end
371 endcase
372 end
373 `DECODE_LDRSTR_UNDEFINED: begin end
374 `DECODE_LDRSTR: if(!inbubble) begin
375 next_write_reg = 1'bx;
376 next_write_num = 4'bxxxx;
377 next_write_data = 32'hxxxxxxxx;
378 case(lsr_state)
379 `LSR_MEMIO: begin
380 next_write_reg = insn[20] /* L */;
381 next_write_num = insn[15:12];
382 if(insn[20] /* L */) begin
383 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
384 end
385 end
386 `LSR_STRB_WR:
387 next_write_reg = 1'b0;
388 `LSR_BASEWB: begin
389 next_write_reg = 1'b1;
390 next_write_num = insn[19:16];
391 next_write_data = addr;
392 end
393 `LSR_WBFLUSH:
394 next_write_reg = 1'b0;
395 default: begin end
396 endcase
397 end
398 `DECODE_LDMSTM: if(!inbubble) begin
399 next_write_reg = 1'bx;
400 next_write_num = 4'bxxxx;
401 next_write_data = 32'hxxxxxxxx;
402 case(lsm_state)
403 `LSM_SETUP:
404 next_write_reg = 1'b0;
405 `LSM_MEMIO: begin
fa42d706 406 if(insn[20] /* L */) begin
1ce42ada
JW
407 next_write_reg = !rw_wait;
408 next_write_num = cur_reg;
409 next_write_data = rd_data;
410 end else
411 next_write_reg = 1'b0;
412 end
413 `LSM_BASEWB: begin
414 next_write_reg = insn[21] /* writeback */;
415 next_write_num = insn[19:16];
416 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
417 if(cur_reg == 4'hF && insn[22]) begin
418 next_outcpsr = spsr;
419 next_outcpsrup = 1;
420 end
421 end
422 `LSM_WBFLUSH:
423 next_write_reg = 1'b0;
424 default: begin end
425 endcase
426 end
427 `DECODE_MRCMCR: if(!inbubble) begin
428 next_write_reg = 1'bx;
429 next_write_num = 4'bxxxx;
430 next_write_data = 32'hxxxxxxxx;
431 next_outcpsr = 32'hxxxxxxxx;
432 next_outcpsrup = 1'bx;
433 if (insn[20] == 1 /* load from coprocessor */)
434 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
435 next_write_reg = 1'b1;
436 next_write_num = insn[15:12];
437 next_write_data = cp_read;
438 end else begin
439 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
440 next_outcpsrup = 1;
441 end
442 end
443 endcase
444 end
445
50d1792c 446 /* Bus/address control logic. */
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CL
447 always @(*)
448 begin
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CL
449 rd_req = 1'b0;
450 wr_req = 1'b0;
463f8162
JW
451 offset = prev_offset;
452 addr = prevaddr;
453 raddr = 32'hxxxxxxxx;
b3bb2fb8 454 busaddr = 32'hxxxxxxxx;
2bcc55d5 455 data_size = 3'bxxx;
1ce42ada 456
d73619a2 457 casez(insn)
5989b2f5 458 `DECODE_ALU_SWP: if(!inbubble) begin
5989b2f5 459 busaddr = {op0[31:2], 2'b0};
2bcc55d5 460 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 461 case(swp_state)
33bb0152 462 `SWP_READING:
5989b2f5 463 rd_req = 1'b1;
50d1792c 464 `SWP_WRITING:
5989b2f5 465 wr_req = 1'b1;
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CL
466 default: begin end
467 endcase
9a0d0e43 468 end
fb529aac 469 `DECODE_ALU_MULT: begin end
666ceb03
CL
470 `DECODE_ALU_HDATA_REG,
471 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
463f8162
JW
472 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
473 raddr = insn[24] ? op0 : addr; /* pre/post increment */
666ceb03
CL
474 busaddr = raddr;
475 /* rotate to correct position */
476 case(insn[6:5])
50d1792c 477 2'b01: /* unsigned half */
2bcc55d5 478 data_size = 3'b010;
50d1792c 479 2'b10: /* signed byte */
2bcc55d5 480 data_size = 3'b001;
50d1792c 481 2'b11: /* signed half */
2bcc55d5 482 data_size = 3'b010;
ab12fa63 483 default: begin
ab12fa63 484 data_size = 3'bxxx;
ab12fa63 485 end
666ceb03 486 endcase
33bb0152 487
666ceb03 488 case(lsrh_state)
ab12fa63 489 `LSRH_MEMIO: begin
666ceb03
CL
490 rd_req = insn[20];
491 wr_req = ~insn[20];
666ceb03 492 end
33bb0152 493 `LSRH_BASEWB: begin end
1ce42ada 494 `LSRH_WBFLUSH: begin end
666ceb03
CL
495 default: begin end
496 endcase
497 end
b3bb2fb8 498 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 499 `DECODE_LDRSTR: if(!inbubble) begin
463f8162
JW
500 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
501 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 502 busaddr = raddr;
2bcc55d5 503 data_size = insn[22] ? 3'b001 : 3'b100;
33bb0152 504 case (lsr_state)
ab12fa63 505 `LSR_MEMIO: begin
6d18bf27
JW
506 rd_req = insn[20] /* L */ || insn[22] /* B */;
507 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
b3bb2fb8 508 end
50d1792c 509 `LSR_STRB_WR:
6d18bf27 510 wr_req = 1;
33bb0152
JW
511 `LSR_BASEWB: begin end
512 `LSR_WBFLUSH: begin end
513 default: begin end
514 endcase
515 end
516 `DECODE_LDMSTM: if (!inbubble) begin
517 data_size = 3'b100;
518 case (lsm_state)
463f8162
JW
519 `LSM_SETUP:
520 offset = 6'b0;
33bb0152
JW
521 `LSM_MEMIO: begin
522 rd_req = insn[20];
523 wr_req = ~insn[20];
463f8162
JW
524 offset = prev_offset + 6'h4;
525 offset_sel = insn[24] ? offset : prev_offset;
526 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
33bb0152 527 busaddr = raddr;
4d7253f1 528 end
33bb0152
JW
529 `LSM_BASEWB: begin end
530 `LSM_WBFLUSH: begin end
531 default: begin end
532 endcase
533 end
534 `DECODE_LDCSTC: begin end
535 `DECODE_CDP: begin end
536 `DECODE_MRCMCR: begin end
537 default: begin end
538 endcase
539 end
540
50d1792c 541 /* Bus data control logic. */
33bb0152
JW
542 always @(*)
543 begin
50d1792c 544 wr_data = 32'hxxxxxxxx;
33bb0152 545
33bb0152 546 casez(insn)
50d1792c
JW
547 `DECODE_ALU_SWP: if(!inbubble)
548 if (swp_state == `SWP_WRITING)
549 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
33bb0152
JW
550 `DECODE_ALU_MULT: begin end
551 `DECODE_ALU_HDATA_REG,
50d1792c 552 `DECODE_ALU_HDATA_IMM: if(!inbubble)
33bb0152 553 case(insn[6:5])
50d1792c
JW
554 2'b01: /* unsigned half */
555 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
556 2'b10: /* signed byte */
557 wr_data = {4{op2[7:0]}};
558 2'b11: /* signed half */
559 wr_data = {2{op2[15:0]}};
33bb0152
JW
560 default: begin end
561 endcase
33bb0152
JW
562 `DECODE_LDRSTR_UNDEFINED: begin end
563 `DECODE_LDRSTR: if(!inbubble) begin
50d1792c
JW
564 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
565 if (lsr_state == `LSR_STRB_WR)
566 case (busaddr[1:0])
567 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
568 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
569 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
570 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
571 endcase
b3bb2fb8 572 end
50d1792c 573 `DECODE_LDMSTM: if (!inbubble)
e92804b3 574 if (lsm_state == `LSM_MEMIO)
50d1792c
JW
575 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
576 `DECODE_LDCSTC: begin end
577 `DECODE_CDP: begin end
578 `DECODE_MRCMCR: begin end
579 default: begin end
580 endcase
581 end
582
583 /* LDM/STM register control logic. */
e54a317f 584 always @(posedge clk)
8e30fdaf 585 if (!rw_wait || lsm_state != `LSM_MEMIO)
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JW
586 begin
587 prev_reg <= cur_reg;
588 regs <= next_regs;
589 end
590
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JW
591 always @(*)
592 begin
e92804b3 593 st_read = 4'hx;
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JW
594 cur_reg = prev_reg;
595 next_regs = regs;
596
597 casez(insn)
5989b2f5 598 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 599 case(lsm_state)
50d1792c 600 `LSM_SETUP:
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JW
601 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
602 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
bb2595ed 603 `LSM_MEMIO: begin
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CL
604 casez(regs)
605 16'b???????????????1: begin
e08b748a 606 cur_reg = 4'h0;
b114e03f 607 next_regs = {regs[15:1], 1'b0};
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CL
608 end
609 16'b??????????????10: begin
e08b748a 610 cur_reg = 4'h1;
b114e03f 611 next_regs = {regs[15:2], 2'b0};
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CL
612 end
613 16'b?????????????100: begin
e08b748a 614 cur_reg = 4'h2;
b114e03f 615 next_regs = {regs[15:3], 3'b0};
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CL
616 end
617 16'b????????????1000: begin
e08b748a 618 cur_reg = 4'h3;
b114e03f 619 next_regs = {regs[15:4], 4'b0};
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CL
620 end
621 16'b???????????10000: begin
e08b748a 622 cur_reg = 4'h4;
b114e03f 623 next_regs = {regs[15:5], 5'b0};
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CL
624 end
625 16'b??????????100000: begin
e08b748a 626 cur_reg = 4'h5;
b114e03f 627 next_regs = {regs[15:6], 6'b0};
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CL
628 end
629 16'b?????????1000000: begin
e08b748a 630 cur_reg = 4'h6;
b114e03f 631 next_regs = {regs[15:7], 7'b0};
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CL
632 end
633 16'b????????10000000: begin
e08b748a 634 cur_reg = 4'h7;
b114e03f 635 next_regs = {regs[15:8], 8'b0};
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CL
636 end
637 16'b???????100000000: begin
e08b748a 638 cur_reg = 4'h8;
b114e03f 639 next_regs = {regs[15:9], 9'b0};
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CL
640 end
641 16'b??????1000000000: begin
e08b748a 642 cur_reg = 4'h9;
b114e03f 643 next_regs = {regs[15:10], 10'b0};
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CL
644 end
645 16'b?????10000000000: begin
e08b748a 646 cur_reg = 4'hA;
b114e03f 647 next_regs = {regs[15:11], 11'b0};
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CL
648 end
649 16'b????100000000000: begin
e08b748a 650 cur_reg = 4'hB;
b114e03f 651 next_regs = {regs[15:12], 12'b0};
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CL
652 end
653 16'b???1000000000000: begin
e08b748a 654 cur_reg = 4'hC;
b114e03f 655 next_regs = {regs[15:13], 13'b0};
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CL
656 end
657 16'b??10000000000000: begin
e08b748a 658 cur_reg = 4'hD;
b114e03f 659 next_regs = {regs[15:14], 14'b0};
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CL
660 end
661 16'b?100000000000000: begin
e08b748a 662 cur_reg = 4'hE;
b114e03f 663 next_regs = {regs[15], 15'b0};
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CL
664 end
665 16'b1000000000000000: begin
e08b748a 666 cur_reg = 4'hF;
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CL
667 next_regs = 16'b0;
668 end
669 default: begin
e08b748a
CL
670 cur_reg = 4'hx;
671 next_regs = 16'b0;
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CL
672 end
673 endcase
b957d34d 674 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
50d1792c 675
b114e03f 676 st_read = cur_reg;
9a0d0e43 677 end
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JW
678 `LSM_BASEWB: begin end
679 `LSM_WBFLUSH: begin end
680 default: begin end
681 endcase
682 end
683 endcase
684 end
685
686 always @(*)
687 begin
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JW
688 do_rd_data_latch = 0;
689
690 next_outbubble = inbubble;
691
692 lsrh_rddata = 32'hxxxxxxxx;
693 lsrh_rddata_s1 = 16'hxxxx;
694 lsrh_rddata_s2 = 8'hxx;
695 next_swp_oldval = swp_oldval;
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JW
696
697 align_s1 = 32'hxxxxxxxx;
698 align_s2 = 32'hxxxxxxxx;
699 align_rddata = 32'hxxxxxxxx;
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700
701 /* XXX shit not given about endianness */
702 casez(insn)
703 `DECODE_ALU_SWP: if(!inbubble) begin
704 next_outbubble = rw_wait;
705 case(swp_state)
706 `SWP_READING:
707 if(!rw_wait)
708 next_swp_oldval = rd_data;
709 `SWP_WRITING: begin end
710 default: begin end
711 endcase
712 end
713 `DECODE_ALU_MULT: begin end
714 `DECODE_ALU_HDATA_REG,
715 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
716 next_outbubble = rw_wait;
717
718 /* rotate to correct position */
719 case(insn[6:5])
720 2'b01: begin /* unsigned half */
721 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
722 end
723 2'b10: begin /* signed byte */
724 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
725 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
726 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
727 end
728 2'b11: begin /* signed half */
729 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
730 end
731 default: begin
732 lsrh_rddata = 32'hxxxxxxxx;
733 end
734 endcase
735
736 case(lsrh_state)
737 `LSRH_MEMIO: begin end
738 `LSRH_BASEWB:
739 next_outbubble = 1'b0;
740 `LSRH_WBFLUSH: begin end
741 default: begin end
742 endcase
743 end
744 `DECODE_LDRSTR_UNDEFINED: begin end
745 `DECODE_LDRSTR: if(!inbubble) begin
746 next_outbubble = rw_wait;
747 /* rotate to correct position */
748 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
749 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
750 /* select byte or word */
751 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
752 case(lsr_state)
753 `LSR_MEMIO:
754 if (insn[22] /* B */ && !insn[20] /* L */)
755 do_rd_data_latch = 1;
756 `LSR_STRB_WR: begin end
757 `LSR_BASEWB:
758 next_outbubble = 0;
759 `LSR_WBFLUSH: begin end
760 default: begin end
761 endcase
762 end
763 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
764 `DECODE_LDMSTM: if(!inbubble) begin
765 next_outbubble = rw_wait;
766 case(lsm_state)
767 `LSM_SETUP: begin end
768 `LSM_MEMIO: begin end
1ce42ada 769 `LSM_BASEWB:
4d7253f1 770 next_outbubble = 0;
bb2595ed 771 `LSM_WBFLUSH: begin end
d73619a2 772 default: $stop;
9a0d0e43 773 endcase
43e4332c 774 end
bb2595ed 775 `DECODE_LDCSTC: begin end
5989b2f5 776 `DECODE_CDP: if(!inbubble) begin
43e4332c 777 if (cp_busy) begin
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JW
778 next_outbubble = 1;
779 end
43e4332c 780 end
5989b2f5 781 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c 782 if (cp_busy) begin
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JW
783 next_outbubble = 1;
784 end
43e4332c 785 end
b3bb2fb8
CL
786 default: begin end
787 endcase
d73619a2
JW
788
789 if ((flush || delayedflush) && !outstall)
790 next_outbubble = 1'b1;
b3bb2fb8 791 end
b3bb2fb8 792endmodule
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