Issue, system, RegFile: First pass at adding resets.
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8 6
ab7ee9fc
JW
7 input flush,
8
b3bb2fb8
CL
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
9fc6c23c 16 output reg [2:0] data_size,
b3bb2fb8
CL
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
a02ca509 21
979f2bd7
JW
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
804dc0bc 26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
979f2bd7 29
a02ca509
JW
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
e68b2378
JW
34 input [31:0] op0,
35 input [31:0] op1,
6d0f9d82 36 input [31:0] op2,
efd1aa13
CL
37 input [31:0] spsr,
38 input [31:0] cpsr,
fdecc897 39 input cpsrup,
a02ca509
JW
40 input write_reg,
41 input [3:0] write_num,
42 input [31:0] write_data,
b3bb2fb8 43
a02ca509
JW
44 /* outputs */
45 output reg outstall,
46 output reg outbubble,
b3bb2fb8 47 output reg [31:0] outpc,
a02ca509
JW
48 output reg [31:0] outinsn,
49 output reg out_write_reg = 1'b0,
50 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 51 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 52 output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897
JW
53 output reg [31:0] outcpsr = 32'hxxxxxxxx,
54 output reg outcpsrup = 1'hx
a02ca509 55 );
b3bb2fb8 56
efd1aa13 57 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 58 reg next_outcpsrup;
666ceb03 59 reg [31:0] prevaddr;
e08b748a 60 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 61 reg next_writeback;
e08b748a 62
804dc0bc
JW
63 reg next_outbubble;
64 reg next_write_reg;
65 reg [3:0] next_write_num;
66 reg [31:0] next_write_data;
74d3729c 67
6d18bf27 68 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
666ceb03
CL
69 reg [31:0] align_s1, align_s2, align_rddata;
70
4d7253f1 71 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03
CL
72 reg [31:0] lsrh_rddata;
73 reg [15:0] lsrh_rddata_s1;
74 reg [7:0] lsrh_rddata_s2;
9a0d0e43 75
b783a475 76 reg [15:0] regs, next_regs;
4d7253f1 77 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 78 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 79
9a0d0e43
CL
80 reg [31:0] swp_oldval, next_swp_oldval;
81 reg [1:0] swp_state = 2'b01, next_swp_state;
6d18bf27
JW
82
83 reg do_rd_data_latch;
84 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
a02ca509
JW
85
86 always @(posedge clk)
87 begin
88 outpc <= pc;
89 outinsn <= insn;
c65110a8
JW
90 outbubble <= next_outbubble;
91 out_write_reg <= next_write_reg;
92 out_write_num <= next_write_num;
93 out_write_data <= next_write_data;
e68b2378 94 regs <= next_regs;
e08b748a 95 prev_reg <= cur_reg;
95704fd3
JW
96 if (!rw_wait)
97 prev_offset <= offset;
b114e03f 98 prev_raddr <= raddr;
ab7ee9fc
JW
99 outcpsr <= next_outcpsr;
100 outspsr <= spsr;
fdecc897 101 outcpsrup <= next_outcpsrup;
9a0d0e43 102 swp_state <= next_swp_state;
666ceb03
CL
103 lsm_state <= next_lsm_state;
104 lsr_state <= next_lsr_state;
105 lsrh_state <= next_lsrh_state;
6d18bf27
JW
106 if (do_rd_data_latch)
107 rd_data_latch <= rd_data;
666ceb03 108 prevaddr <= addr;
a02ca509 109 end
d73619a2
JW
110
111 reg delayedflush = 0;
112 always @(posedge clk)
113 if (flush && outstall /* halp! I can't do it now, maybe later? */)
114 delayedflush <= 1;
115 else if (!outstall /* anything has been handled this time around */)
116 delayedflush <= 0;
b3bb2fb8
CL
117
118 always @(*)
119 begin
666ceb03 120 addr = prevaddr;
b3bb2fb8
CL
121 raddr = 32'hxxxxxxxx;
122 rd_req = 1'b0;
123 wr_req = 1'b0;
124 wr_data = 32'hxxxxxxxx;
125 busaddr = 32'hxxxxxxxx;
2bcc55d5 126 data_size = 3'bxxx;
b3bb2fb8 127 outstall = 1'b0;
cc1ce5b3 128 st_read = 4'hx;
6d18bf27 129 do_rd_data_latch = 0;
a02ca509
JW
130 next_write_reg = write_reg;
131 next_write_num = write_num;
132 next_write_data = write_data;
c65110a8 133 next_outbubble = inbubble;
9a0d0e43 134 next_regs = regs;
979f2bd7 135 cp_req = 1'b0;
43e4332c
JW
136 cp_rnw = 1'bx;
137 cp_write = 32'hxxxxxxxx;
b114e03f 138 offset = prev_offset;
4d7253f1 139 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
fdecc897 140 next_outcpsrup = cpsrup;
666ceb03 141 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
142 lsrh_rddata_s1 = 16'hxxxx;
143 lsrh_rddata_s2 = 8'hxx;
9a0d0e43
CL
144 next_lsm_state = lsm_state;
145 next_lsr_state = lsr_state;
666ceb03 146 next_lsrh_state = lsrh_state;
9a0d0e43
CL
147 next_swp_oldval = swp_oldval;
148 next_swp_state = swp_state;
149 cur_reg = prev_reg;
9f082c0b 150
5989b2f5 151 /* XXX shit not given about endianness */
d73619a2 152 casez(insn)
5989b2f5
CL
153 `DECODE_ALU_SWP: if(!inbubble) begin
154 outstall = rw_wait;
155 next_outbubble = rw_wait;
156 busaddr = {op0[31:2], 2'b0};
2bcc55d5 157 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5
CL
158 case(swp_state)
159 2'b01: begin
160 rd_req = 1'b1;
161 outstall = 1'b1;
162 if(!rw_wait) begin
163 next_swp_state = 2'b10;
164 next_swp_oldval = rd_data;
9a0d0e43 165 end
fb529aac 166 $display("SWP: read stage");
9a0d0e43 167 end
5989b2f5
CL
168 2'b10: begin
169 wr_req = 1'b1;
2bcc55d5 170 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
171 next_write_reg = 1'b1;
172 next_write_num = insn[15:12];
2bcc55d5 173 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5
CL
174 if(!rw_wait)
175 next_swp_state = 2'b01;
fb529aac 176 $display("SWP: write stage");
5989b2f5
CL
177 end
178 default: begin end
179 endcase
9a0d0e43 180 end
fb529aac 181 `DECODE_ALU_MULT: begin end
666ceb03
CL
182 `DECODE_ALU_HDATA_REG,
183 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
184 next_outbubble = rw_wait;
185 outstall = rw_wait;
186 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
187 raddr = insn[24] ? op0 : addr; /* pre/post increment */
188 busaddr = raddr;
189 /* rotate to correct position */
190 case(insn[6:5])
191 2'b00: begin end /* swp */
192 2'b01: begin /* unsigned half */
193 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 194 data_size = 3'b010;
666ceb03
CL
195 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
196 end
197 2'b10: begin /* signed byte */
198 wr_data = {4{op2[7:0]}};
2bcc55d5 199 data_size = 3'b001;
666ceb03
CL
200 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
201 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
202 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
203 end
204 2'b11: begin /* signed half */
205 wr_data = {2{op2[15:0]}};
2bcc55d5 206 data_size = 3'b010;
666ceb03
CL
207 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
208 end
209 endcase
210
211 case(lsrh_state)
4d7253f1 212 3'b001: begin
666ceb03
CL
213 rd_req = insn[20];
214 wr_req = ~insn[20];
215 next_write_num = insn[15:12];
216 next_write_data = lsrh_rddata;
217 if(insn[20]) begin
218 next_write_reg = 1'b1;
219 end
d64d6ef9 220 if(insn[21] | !insn[24]) begin
666ceb03
CL
221 outstall = 1'b1;
222 if(!rw_wait)
4d7253f1 223 next_lsrh_state = 3'b010;
666ceb03 224 end
fb529aac 225 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
666ceb03 226 end
4d7253f1
JW
227 3'b010: begin
228 next_outbubble = 1'b0;
666ceb03
CL
229 next_write_reg = 1'b1;
230 next_write_num = insn[19:16];
231 next_write_data = addr;
4d7253f1
JW
232 next_lsrh_state = 3'b100;
233 end
234 3'b100: begin
235 outstall = 0;
236 next_lsrh_state = 3'b001;
666ceb03
CL
237 end
238 default: begin end
239 endcase
d64d6ef9
JW
240
241 if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
242 outstall = 1'b0;
243 next_lsrh_state = 3'b001;
244 end
666ceb03 245 end
b3bb2fb8 246 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
247 `DECODE_LDRSTR: if(!inbubble) begin
248 next_outbubble = rw_wait;
249 outstall = rw_wait;
250 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 251 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
252 busaddr = raddr;
253 /* rotate to correct position */
5989b2f5
CL
254 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
255 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
256 /* select byte or word */
257 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
6d18bf27 258 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5 259 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 260 case(lsr_state)
6d18bf27
JW
261 4'b0001: begin
262 rd_req = insn[20] /* L */ || insn[22] /* B */;
263 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
fb529aac 264 next_write_reg = insn[20] /* L */;
666ceb03 265 next_write_num = insn[15:12];
fb529aac 266 if(insn[20] /* L */) begin
6d18bf27 267 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
a02ca509 268 end
6d18bf27
JW
269 if (insn[22] /* B */ && !insn[20] /* L */) begin
270 do_rd_data_latch = 1;
271 outstall = 1'b1;
272 if (!rw_wait)
273 next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
274 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
5989b2f5
CL
275 outstall = 1'b1;
276 if(!rw_wait)
6d18bf27 277 next_lsr_state = 4'b0100;
a02ca509 278 end
d73619a2 279 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8 280 end
6d18bf27
JW
281 4'b0010: begin
282 $display("LDRSTR: Handling STRB");
4d7253f1 283 outstall = 1;
6d18bf27
JW
284 rd_req = 0;
285 wr_req = 1;
286 next_write_reg = 0;
287 case (busaddr[1:0])
288 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
289 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
290 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
291 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
292 endcase
293 if(insn[21] /* W */ | !insn[24] /* P */) begin
294 if(!rw_wait)
295 next_lsr_state = 4'b0100;
296 end else if (!rw_wait)
297 next_lsr_state = 4'b1000;
298 end
299 4'b0100: begin
300 outstall = 1;
301 rd_req = 0;
302 wr_req= 0;
4d7253f1 303 next_outbubble = 0;
5989b2f5
CL
304 next_write_reg = 1'b1;
305 next_write_num = insn[19:16];
306 next_write_data = addr;
6d18bf27 307 next_lsr_state = 4'b1000;
4d7253f1 308 end
6d18bf27
JW
309 4'b1000: begin
310 rd_req = 0;
311 wr_req= 0;
4d7253f1 312 outstall = 0;
6d18bf27 313 next_lsr_state = 4'b0001;
5989b2f5
CL
314 end
315 default: begin end
316 endcase
d64d6ef9 317
6d18bf27 318 if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
d64d6ef9 319 outstall = 1'b0;
6d18bf27 320 next_lsr_state = 4'b0001;
d64d6ef9 321 end
b3bb2fb8 322 end
5989b2f5
CL
323 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
324 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43
CL
325 outstall = rw_wait;
326 next_outbubble = rw_wait;
2bcc55d5 327 data_size = 3'b100;
9a0d0e43 328 case(lsm_state)
4d7253f1 329 4'b0001: begin
b114e03f
CL
330// next_regs = insn[23] ? op1[15:0] : op1[0:15];
331 /** verilator can suck my dick */
b957d34d
JW
332 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
333 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
334 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 335 offset = 6'b0;
d64d6ef9
JW
336 outstall = 1'b1;
337 next_lsm_state = 4'b0010;
e08b748a 338 end
4d7253f1 339 4'b0010: begin
9a0d0e43
CL
340 rd_req = insn[20];
341 wr_req = ~insn[20];
9f082c0b
CL
342 casez(regs)
343 16'b???????????????1: begin
e08b748a 344 cur_reg = 4'h0;
b114e03f 345 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
346 end
347 16'b??????????????10: begin
e08b748a 348 cur_reg = 4'h1;
b114e03f 349 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
350 end
351 16'b?????????????100: begin
e08b748a 352 cur_reg = 4'h2;
b114e03f 353 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
354 end
355 16'b????????????1000: begin
e08b748a 356 cur_reg = 4'h3;
b114e03f 357 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
358 end
359 16'b???????????10000: begin
e08b748a 360 cur_reg = 4'h4;
b114e03f 361 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
362 end
363 16'b??????????100000: begin
e08b748a 364 cur_reg = 4'h5;
b114e03f 365 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
366 end
367 16'b?????????1000000: begin
e08b748a 368 cur_reg = 4'h6;
b114e03f 369 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
370 end
371 16'b????????10000000: begin
e08b748a 372 cur_reg = 4'h7;
b114e03f 373 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
374 end
375 16'b???????100000000: begin
e08b748a 376 cur_reg = 4'h8;
b114e03f 377 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
378 end
379 16'b??????1000000000: begin
e08b748a 380 cur_reg = 4'h9;
b114e03f 381 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
382 end
383 16'b?????10000000000: begin
e08b748a 384 cur_reg = 4'hA;
b114e03f 385 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
386 end
387 16'b????100000000000: begin
e08b748a 388 cur_reg = 4'hB;
b114e03f 389 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
390 end
391 16'b???1000000000000: begin
e08b748a 392 cur_reg = 4'hC;
b114e03f 393 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
394 end
395 16'b??10000000000000: begin
e08b748a 396 cur_reg = 4'hD;
b114e03f 397 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
398 end
399 16'b?100000000000000: begin
e08b748a 400 cur_reg = 4'hE;
b114e03f 401 next_regs = {regs[15], 15'b0};
9f082c0b
CL
402 end
403 16'b1000000000000000: begin
e08b748a 404 cur_reg = 4'hF;
9f082c0b
CL
405 next_regs = 16'b0;
406 end
407 default: begin
e08b748a
CL
408 cur_reg = 4'hx;
409 next_regs = 16'b0;
9f082c0b
CL
410 end
411 endcase
b957d34d 412 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13
CL
413 if(cur_reg == 4'hF && insn[22]) begin
414 next_outcpsr = spsr;
fdecc897 415 next_outcpsrup = 1;
efd1aa13 416 end
b114e03f 417
95704fd3 418 offset = prev_offset + 6'h4;
d73619a2
JW
419 offset_sel = insn[24] ? offset : prev_offset;
420 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
421 if(insn[20]) begin
422 next_write_reg = !rw_wait;
423 next_write_num = cur_reg;
424 next_write_data = rd_data;
425 end
426 if (rw_wait) begin
427 next_regs = regs;
428 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
429 end
430
431 st_read = cur_reg;
b957d34d 432 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 433 busaddr = raddr;
b957d34d 434
d73619a2 435 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43
CL
436
437 outstall = 1'b1;
438
439 if(next_regs == 16'b0) begin
4d7253f1 440 next_lsm_state = 4'b0100;
9a0d0e43
CL
441 end
442 end
4d7253f1
JW
443 4'b0100: begin
444 outstall = 1;
445 next_outbubble = 0;
b957d34d 446 next_write_reg = insn[21] /* writeback */;
9a0d0e43
CL
447 next_write_num = insn[19:16];
448 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
4d7253f1 449 next_lsm_state = 4'b1000;
d73619a2 450 $display("LDMSTM: Stage 3: Writing back");
b783a475 451 end
4d7253f1
JW
452 4'b1000: begin
453 outstall = 0;
454 next_lsm_state = 4'b0001;
455 end
d73619a2 456 default: $stop;
9a0d0e43 457 endcase
d64d6ef9
JW
458 if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
459 outstall = 1'b0;
460 next_lsm_state = 4'b0001;
461 end
d73619a2 462 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8 463 end
5989b2f5 464 `DECODE_LDCSTC: if(!inbubble) begin
43e4332c
JW
465 $display("WARNING: Unimplemented LDCSTC");
466 end
5989b2f5 467 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
468 cp_req = 1;
469 if (cp_busy) begin
470 outstall = 1;
471 next_outbubble = 1;
472 end
473 if (!cp_ack) begin
474 /* XXX undefined instruction trap */
475 $display("WARNING: Possible CDP undefined instruction");
476 end
477 end
5989b2f5 478 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
479 cp_req = 1;
480 cp_rnw = insn[20] /* L */;
481 if (insn[20] == 0 /* store to coprocessor */)
482 cp_write = op0;
483 else begin
d1d0eb8e
JW
484 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
485 next_write_reg = 1'b1;
486 next_write_num = insn[15:12];
487 next_write_data = cp_read;
fdecc897 488 end else begin
d1d0eb8e 489 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
fdecc897
JW
490 next_outcpsrup = 1;
491 end
43e4332c
JW
492 end
493 if (cp_busy) begin
494 outstall = 1;
495 next_outbubble = 1;
496 end
497 if (!cp_ack) begin
838e283e 498 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 499 end
838e283e 500 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 501 end
b3bb2fb8
CL
502 default: begin end
503 endcase
d73619a2
JW
504
505 if ((flush || delayedflush) && !outstall)
506 next_outbubble = 1'b1;
b3bb2fb8 507 end
b3bb2fb8 508endmodule
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