[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	output reg [31:0] out_cpsr = 32'hxxxxxxxx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg [31:0] prevaddr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;

	wire next_outbubble;	
	wire next_write_reg;
	wire [3:0] next_write_num;
	wire [31:0] next_write_data;

	reg [1:0] lsr_state = 2'b01, next_lsr_state;
	reg [31:0] align_s1, align_s2, align_rddata;

	reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
	reg [31:0] lsrh_rddata;
	reg [15:0] lsrh_rddata_s1;
	reg [7:0] lsrh_rddata_s2;

	reg [15:0] regs, next_regs;
	reg [2:0] lsm_state = 3'b001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		prev_offset <= offset;
		prev_raddr <= raddr;
		out_cpsr <= next_outcpsr;
		out_spsr <= spsr;
		swp_state <= next_swp_state;
		lsm_state <= next_lsm_state;
		lsr_state <= next_lsr_state;
		lsrh_state <= next_lsrh_state;
		prevaddr <= addr;
	end

	always @(*)
	begin
		addr = prevaddr;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		outstall = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		outstall = 1'b0;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
		lsrh_rddata = 32'hxxxxxxxx;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_lsrh_state = lsrh_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		/* XXX shit not given about endianness */
		/* TODO ldrh/strh */
		casez(insn)
		`DECODE_ALU_SWP: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			busaddr = {op0[31:2], 2'b0};
			case(swp_state)
			2'b01: begin
				rd_req = 1'b1;
				outstall = 1'b1;
				if(!rw_wait) begin
					next_swp_state = 2'b10;
					next_swp_oldval = rd_data;
				end
			end
			2'b10: begin
				wr_req = 1'b1;
				wr_data = op1;
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = swp_oldval;
				if(!rw_wait)
					next_swp_state = 2'b01;
			end
			default: begin end
			endcase
		end
		`DECODE_ALU_HDATA_REG,
		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			case(insn[6:5])
			2'b00: begin end /* swp */
			2'b01: begin /* unsigned half */
				wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
				lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
			end
			2'b10: begin /* signed byte */
				wr_data = {4{op2[7:0]}};
				lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
				lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
				lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
			end
			2'b11: begin /* signed half */
				wr_data = {2{op2[15:0]}};
				lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
			end
			endcase

			case(lsrh_state)
			2'b01: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_num = insn[15:12];
				next_write_data = lsrh_rddata;
				if(insn[20]) begin
					next_write_reg = 1'b1;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsrh_state = 2'b10;
				end
			end
			2'b10: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsrh_state = 2'b10;
			end
			default: begin end
			endcase
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
			/* select byte or word */
			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
			wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
			case(lsr_state)
			2'b01: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				if(insn[20]) begin
					next_write_data = align_rddata;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsr_state = 2'b10;
				end
			end
			2'b10: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsr_state = 2'b10;
			end
			default: begin end
			endcase
		end
		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
		`DECODE_LDMSTM: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			case(lsm_state)
			3'b001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                    op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 3'b010;
			end
			3'b010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
				end

				if(rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;
					raddr = prev_raddr;
				end
				else begin
					offset = prev_offset + 6'h4;
					offset_sel = insn[24] ? offset : prev_offset;
					raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
					if(insn[20]) begin
						next_write_reg = 1'b1;
						next_write_num = cur_reg;
						next_write_data = rd_data;
					end
				end

				st_read = cur_reg;
				wr_data = st_data;
				busaddr = raddr;

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 3'b100;
				end
			end
			3'b100: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 3'b001;
			end
			default: begin end
			endcase
		end
		`DECODE_LDCSTC: if(!inbubble) begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: if(!inbubble) begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: if(!inbubble) begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = cp_read;
				end else
					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
			end
			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
		end
		default: begin end
		endcase
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8 CL	6
	7	/* bus interface */
	8	output reg [31:0] busaddr,
	9	output reg rd_req,
	10	output reg wr_req,
	11	input rw_wait,
	12	output reg [31:0] wr_data,
	13	input [31:0] rd_data,
	14
	15	/* regfile interface */
	16	output reg [3:0] st_read,
	17	input [31:0] st_data,
a02ca509	18
979f2bd7 JW	19	/* Coprocessor interface */
	20	output reg cp_req,
	21	input cp_ack,
	22	input cp_busy,
43e4332c JW	23	output cp_rnw, /* 1 = read from CP, 0 = write to CP */
	24	input [31:0] cp_read,
	25	output reg [31:0] cp_write,
979f2bd7	26
a02ca509 JW	27	/* stage inputs */
	28	input inbubble,
	29	input [31:0] pc,
	30	input [31:0] insn,
e68b2378 JW	31	input [31:0] op0,
e68b2378 JW	32	input [31:0] op1,
6d0f9d82	33	input [31:0] op2,
efd1aa13 CL	34	input [31:0] spsr,
efd1aa13 CL	35	input [31:0] cpsr,
a02ca509 JW	36	input write_reg,
	37	input [3:0] write_num,
	38	input [31:0] write_data,
b3bb2fb8	39
a02ca509 JW	40	/* outputs */
	41	output reg outstall,
	42	output reg outbubble,
b3bb2fb8	43	output reg [31:0] outpc,
a02ca509 JW	44	output reg [31:0] outinsn,
	45	output reg out_write_reg = 1'b0,
	46	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 CL	47	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	48	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	49	output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509	50	);
b3bb2fb8	51
efd1aa13	52	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
666ceb03	53	reg [31:0] prevaddr;
e08b748a	54	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	55	reg next_writeback;
e08b748a	56
c65110a8	57	wire next_outbubble;
a02ca509 JW	58	wire next_write_reg;
	59	wire [3:0] next_write_num;
	60	wire [31:0] next_write_data;
74d3729c	61
9a0d0e43	62	reg [1:0] lsr_state = 2'b01, next_lsr_state;
666ceb03 CL	63	reg [31:0] align_s1, align_s2, align_rddata;
	64
	65	reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
	66	reg [31:0] lsrh_rddata;
	67	reg [15:0] lsrh_rddata_s1;
	68	reg [7:0] lsrh_rddata_s2;
9a0d0e43	69
b783a475	70	reg [15:0] regs, next_regs;
9a0d0e43	71	reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f	72	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	73
9a0d0e43 CL	74	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	75	reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509 JW	76
	77	always @(posedge clk)
	78	begin
	79	outpc <= pc;
	80	outinsn <= insn;
c65110a8 JW	81	outbubble <= next_outbubble;
	82	out_write_reg <= next_write_reg;
	83	out_write_num <= next_write_num;
	84	out_write_data <= next_write_data;
e68b2378	85	regs <= next_regs;
e08b748a	86	prev_reg <= cur_reg;
b114e03f CL	87	prev_offset <= offset;
b114e03f CL	88	prev_raddr <= raddr;
efd1aa13 CL	89	out_cpsr <= next_outcpsr;
efd1aa13 CL	90	out_spsr <= spsr;
9a0d0e43	91	swp_state <= next_swp_state;
666ceb03 CL	92	lsm_state <= next_lsm_state;
	93	lsr_state <= next_lsr_state;
	94	lsrh_state <= next_lsrh_state;
	95	prevaddr <= addr;
a02ca509	96	end
b3bb2fb8 CL	97
	98	always @(*)
	99	begin
666ceb03	100	addr = prevaddr;
b3bb2fb8 CL	101	raddr = 32'hxxxxxxxx;
	102	rd_req = 1'b0;
	103	wr_req = 1'b0;
	104	wr_data = 32'hxxxxxxxx;
	105	busaddr = 32'hxxxxxxxx;
	106	outstall = 1'b0;
a02ca509 JW	107	next_write_reg = write_reg;
	108	next_write_num = write_num;
	109	next_write_data = write_data;
c65110a8	110	next_outbubble = inbubble;
a02ca509	111	outstall = 1'b0;
9a0d0e43	112	next_regs = regs;
979f2bd7	113	cp_req = 1'b0;
43e4332c JW	114	cp_rnw = 1'bx;
43e4332c JW	115	cp_write = 32'hxxxxxxxx;
b114e03f	116	offset = prev_offset;
9a0d0e43	117	next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
666ceb03	118	lsrh_rddata = 32'hxxxxxxxx;
9a0d0e43 CL	119	next_lsm_state = lsm_state;
9a0d0e43 CL	120	next_lsr_state = lsr_state;
666ceb03	121	next_lsrh_state = lsrh_state;
9a0d0e43 CL	122	next_swp_oldval = swp_oldval;
	123	next_swp_state = swp_state;
	124	cur_reg = prev_reg;
9f082c0b	125
5989b2f5 CL	126	/* XXX shit not given about endianness */
5989b2f5 CL	127	/* TODO ldrh/strh */
b3bb2fb8	128	casez(insn)
5989b2f5 CL	129	`DECODE_ALU_SWP: if(!inbubble) begin
	130	outstall = rw_wait;
	131	next_outbubble = rw_wait;
	132	busaddr = {op0[31:2], 2'b0};
	133	case(swp_state)
	134	2'b01: begin
	135	rd_req = 1'b1;
	136	outstall = 1'b1;
	137	if(!rw_wait) begin
	138	next_swp_state = 2'b10;
	139	next_swp_oldval = rd_data;
9a0d0e43	140	end
9a0d0e43	141	end
5989b2f5 CL	142	2'b10: begin
	143	wr_req = 1'b1;
	144	wr_data = op1;
	145	next_write_reg = 1'b1;
	146	next_write_num = insn[15:12];
	147	next_write_data = swp_oldval;
	148	if(!rw_wait)
	149	next_swp_state = 2'b01;
	150	end
	151	default: begin end
	152	endcase
9a0d0e43	153	end
666ceb03 CL	154	`DECODE_ALU_HDATA_REG,
	155	`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
	156	next_outbubble = rw_wait;
	157	outstall = rw_wait;
	158	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	159	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	160	busaddr = raddr;
	161	/* rotate to correct position */
	162	case(insn[6:5])
	163	2'b00: begin end /* swp */
	164	2'b01: begin /* unsigned half */
	165	wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
	166	lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
	167	end
	168	2'b10: begin /* signed byte */
	169	wr_data = {4{op2[7:0]}};
	170	lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
	171	lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
	172	lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
	173	end
	174	2'b11: begin /* signed half */
	175	wr_data = {2{op2[15:0]}};
	176	lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
	177	end
	178	endcase
	179
	180	case(lsrh_state)
	181	2'b01: begin
	182	rd_req = insn[20];
	183	wr_req = ~insn[20];
	184	next_write_num = insn[15:12];
	185	next_write_data = lsrh_rddata;
	186	if(insn[20]) begin
	187	next_write_reg = 1'b1;
	188	end
	189	if(insn[21] \| !insn[24]) begin
	190	outstall = 1'b1;
	191	if(!rw_wait)
	192	next_lsrh_state = 2'b10;
	193	end
	194	end
	195	2'b10: begin
	196	next_write_reg = 1'b1;
	197	next_write_num = insn[19:16];
	198	next_write_data = addr;
	199	next_lsrh_state = 2'b10;
	200	end
	201	default: begin end
	202	endcase
	203	end
b3bb2fb8	204	`DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 CL	205	`DECODE_LDRSTR: if(!inbubble) begin
	206	next_outbubble = rw_wait;
	207	outstall = rw_wait;
	208	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	209	raddr = insn[24] ? op0 : addr; /* pre/post increment */
666ceb03 CL	210	busaddr = raddr;
666ceb03 CL	211	/* rotate to correct position */
5989b2f5 CL	212	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	213	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	214	/* select byte or word */
	215	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03	216	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
5989b2f5 CL	217	case(lsr_state)
	218	2'b01: begin
	219	rd_req = insn[20];
	220	wr_req = ~insn[20];
666ceb03 CL	221	next_write_reg = 1'b1;
666ceb03 CL	222	next_write_num = insn[15:12];
5989b2f5	223	if(insn[20]) begin
5989b2f5	224	next_write_data = align_rddata;
a02ca509	225	end
666ceb03	226	if(insn[21] \| !insn[24]) begin
5989b2f5 CL	227	outstall = 1'b1;
	228	if(!rw_wait)
	229	next_lsr_state = 2'b10;
a02ca509	230	end
b3bb2fb8	231	end
5989b2f5 CL	232	2'b10: begin
	233	next_write_reg = 1'b1;
	234	next_write_num = insn[19:16];
	235	next_write_data = addr;
	236	next_lsr_state = 2'b10;
	237	end
	238	default: begin end
	239	endcase
b3bb2fb8	240	end
5989b2f5 CL	241	/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
5989b2f5 CL	242	`DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 CL	243	outstall = rw_wait;
	244	next_outbubble = rw_wait;
	245	case(lsm_state)
	246	3'b001: begin
b114e03f CL	247	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
	248	/** verilator can suck my dick */
	249	next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	250	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
	251	offset = 6'b0;
9a0d0e43 CL	252	outstall = 1'b1;
9a0d0e43 CL	253	next_lsm_state = 3'b010;
e08b748a	254	end
9a0d0e43 CL	255	3'b010: begin
	256	rd_req = insn[20];
	257	wr_req = ~insn[20];
9f082c0b CL	258	casez(regs)
9f082c0b CL	259	16'b???????????????1: begin
e08b748a	260	cur_reg = 4'h0;
b114e03f	261	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	262	end
9f082c0b CL	263	16'b??????????????10: begin
e08b748a	264	cur_reg = 4'h1;
b114e03f	265	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	266	end
9f082c0b CL	267	16'b?????????????100: begin
e08b748a	268	cur_reg = 4'h2;
b114e03f	269	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	270	end
9f082c0b CL	271	16'b????????????1000: begin
e08b748a	272	cur_reg = 4'h3;
b114e03f	273	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	274	end
9f082c0b CL	275	16'b???????????10000: begin
e08b748a	276	cur_reg = 4'h4;
b114e03f	277	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	278	end
9f082c0b CL	279	16'b??????????100000: begin
e08b748a	280	cur_reg = 4'h5;
b114e03f	281	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	282	end
9f082c0b CL	283	16'b?????????1000000: begin
e08b748a	284	cur_reg = 4'h6;
b114e03f	285	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	286	end
9f082c0b CL	287	16'b????????10000000: begin
e08b748a	288	cur_reg = 4'h7;
b114e03f	289	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	290	end
9f082c0b CL	291	16'b???????100000000: begin
e08b748a	292	cur_reg = 4'h8;
b114e03f	293	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	294	end
9f082c0b CL	295	16'b??????1000000000: begin
e08b748a	296	cur_reg = 4'h9;
b114e03f	297	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	298	end
9f082c0b CL	299	16'b?????10000000000: begin
e08b748a	300	cur_reg = 4'hA;
b114e03f	301	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	302	end
9f082c0b CL	303	16'b????100000000000: begin
e08b748a	304	cur_reg = 4'hB;
b114e03f	305	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	306	end
9f082c0b CL	307	16'b???1000000000000: begin
e08b748a	308	cur_reg = 4'hC;
b114e03f	309	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	310	end
9f082c0b CL	311	16'b??10000000000000: begin
e08b748a	312	cur_reg = 4'hD;
b114e03f	313	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	314	end
9f082c0b CL	315	16'b?100000000000000: begin
e08b748a	316	cur_reg = 4'hE;
b114e03f	317	next_regs = {regs[15], 15'b0};
9f082c0b CL	318	end
9f082c0b CL	319	16'b1000000000000000: begin
e08b748a	320	cur_reg = 4'hF;
9f082c0b CL	321	next_regs = 16'b0;
	322	end
	323	default: begin
e08b748a CL	324	cur_reg = 4'hx;
e08b748a CL	325	next_regs = 16'b0;
9f082c0b CL	326	end
9f082c0b CL	327	endcase
b114e03f	328	cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
efd1aa13 CL	329	if(cur_reg == 4'hF && insn[22]) begin
	330	next_outcpsr = spsr;
	331	end
b114e03f	332
9a0d0e43 CL	333	if(rw_wait) begin
	334	next_regs = regs;
	335	cur_reg = prev_reg;
	336	raddr = prev_raddr;
	337	end
	338	else begin
	339	offset = prev_offset + 6'h4;
	340	offset_sel = insn[24] ? offset : prev_offset;
	341	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	342	if(insn[20]) begin
	343	next_write_reg = 1'b1;
	344	next_write_num = cur_reg;
	345	next_write_data = rd_data;
	346	end
b114e03f CL	347	end
	348
	349	st_read = cur_reg;
	350	wr_data = st_data;
666ceb03	351	busaddr = raddr;
9a0d0e43 CL	352
	353	outstall = 1'b1;
	354
	355	if(next_regs == 16'b0) begin
	356	next_lsm_state = 3'b100;
	357	end
	358	end
	359	3'b100: begin
	360	next_write_reg = 1'b1;
	361	next_write_num = insn[19:16];
	362	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
	363	next_lsm_state = 3'b001;
b783a475	364	end
9a0d0e43 CL	365	default: begin end
9a0d0e43 CL	366	endcase
b3bb2fb8	367	end
5989b2f5	368	`DECODE_LDCSTC: if(!inbubble) begin
43e4332c JW	369	$display("WARNING: Unimplemented LDCSTC");
43e4332c JW	370	end
5989b2f5	371	`DECODE_CDP: if(!inbubble) begin
43e4332c JW	372	cp_req = 1;
	373	if (cp_busy) begin
	374	outstall = 1;
	375	next_outbubble = 1;
	376	end
	377	if (!cp_ack) begin
	378	/* XXX undefined instruction trap */
	379	$display("WARNING: Possible CDP undefined instruction");
	380	end
	381	end
5989b2f5	382	`DECODE_MRCMCR: if(!inbubble) begin
43e4332c JW	383	cp_req = 1;
	384	cp_rnw = insn[20] /* L */;
	385	if (insn[20] == 0 /* store to coprocessor */)
	386	cp_write = op0;
	387	else begin
d1d0eb8e JW	388	if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
	389	next_write_reg = 1'b1;
	390	next_write_num = insn[15:12];
	391	next_write_data = cp_read;
	392	end else
	393	next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c JW	394	end
	395	if (cp_busy) begin
	396	outstall = 1;
	397	next_outbubble = 1;
	398	end
	399	if (!cp_ack) begin
838e283e	400	$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c	401	end
838e283e	402	$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c	403	end
b3bb2fb8 CL	404	default: begin end
	405	endcase
	406	end
b3bb2fb8	407	endmodule