Memory.v: Cleanup pass 1 before integration.
[firearm.git] / Memory.v
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
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6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
14
15 /* regfile interface */
16 output reg [3:0] st_read,
17 input [31:0] st_data,
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18
19 /* stage inputs */
20 input inbubble,
21 input [31:0] pc,
22 input [31:0] insn,
23 input [31:0] base,
24 input [31:0] offset,
25 input write_reg,
26 input [3:0] write_num,
27 input [31:0] write_data,
b3bb2fb8 28
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29 /* outputs */
30 output reg outstall,
31 output reg outbubble,
b3bb2fb8 32 output reg [31:0] outpc,
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33 output reg [31:0] outinsn,
34 output reg out_write_reg = 1'b0,
35 output reg [3:0] out_write_num = 4'bxxxx,
36 output reg [31:0] out_write_data = 32'hxxxxxxxx
37 );
b3bb2fb8 38
5bcb3b7e 39 reg [31:0] addr, raddr, next_regdata;
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40 reg [3:0] next_regsel;
41 reg next_writeback, next_notdone, next_inc_next;
42 reg [31:0] align_s1, align_s2, align_rddata;
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43
44 wire next_write_reg;
45 wire [3:0] next_write_num;
46 wire [31:0] next_write_data;
74d3729c 47
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48 reg notdone = 1'b0;
49 reg inc_next = 1'b0;
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50
51 always @(posedge clk)
52 begin
53 outpc <= pc;
54 outinsn <= insn;
55 outbubble <= rw_wait;
56 out_write_reg <= next_writeback;
57 out_write_num <= next_regsel;
58 out_write_data <= next_regdata;
59 notdone <= next_notdone;
60 inc_next <= next_inc_next;
61 end
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62
63 always @(*)
64 begin
65 addr = 32'hxxxxxxxx;
66 raddr = 32'hxxxxxxxx;
67 rd_req = 1'b0;
68 wr_req = 1'b0;
69 wr_data = 32'hxxxxxxxx;
70 busaddr = 32'hxxxxxxxx;
71 outstall = 1'b0;
74d3729c 72 next_notdone = 1'b0;
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73 next_write_reg = write_reg;
74 next_write_num = write_num;
75 next_write_data = write_data;
74d3729c 76 next_inc_next = 1'b0;
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77 outstall = 1'b0;
78
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79 casez(insn)
80 `DECODE_LDRSTR_UNDEFINED: begin end
81 `DECODE_LDRSTR: begin
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82 if (!inbubble) begin
83 outstall = rw_wait | notdone;
84
85 addr = insn[23] ? base + offset : base - offset; /* up/down select */
86 raddr = insn[24] ? base : addr;
87 busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
88 rd_req = insn[20];
89 wr_req = ~insn[20];
90
91 /* rotate to correct position */
92 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
93 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
94 /* select byte or word */
95 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
96
97 if(!insn[20]) begin
98 st_read = insn[15:12];
99 wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
100 end
101 else if(!inc_next) begin
102 next_write_reg = 1'b1;
103 next_write_num = insn[15:12];
104 next_write_data = align_rddata;
105 next_inc_next = 1'b1;
106 end
107 else if(insn[21]) begin
108 next_write_reg = 1'b1;
109 next_write_num = insn[19:16];
110 next_write_data = addr;
111 end
112 next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8 113 end
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114 end
115 `DECODE_LDMSTM: begin
116 end
117 default: begin end
118 endcase
119 end
b3bb2fb8 120endmodule
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