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descriptionFireARM pipelined ARM-like CPU implementation in Verilog
ownerJoshua Wise
last changeSat, 28 Aug 2010 22:29:06 +0000 (18:29 -0400)
URLhttp://git.joshuawise.com/git/firearm.git
git+ssh://git.joshuawise.com/storage/git/firearm.git
/nfs/nyus/storage/git/firearm.git
shortlog
2010-08-28 Joshua WiseAdd chip enable correctness for CellularRAM. master msater commit | commitdiff | tree | snapshot
2010-03-12 Joshua WiseAdd support for CellularRAM on Nexys2. commit | commitdiff | tree | snapshot
2010-03-11 Joshua WiseDCache: Rename more internal wires. commit | commitdiff | tree | snapshot
2010-03-11 Joshua Wisesystem: Correct routing regressions from renames. commit | commitdiff | tree | snapshot
2010-03-11 Joshua WiseRegFile: I/O rename commit | commitdiff | tree | snapshot
2010-03-11 Joshua WiseDCache: I/O rename commit | commitdiff | tree | snapshot
2010-03-11 Joshua WiseMemory: Input renaming pass. commit | commitdiff | tree | snapshot
2010-03-11 Joshua WiseExecute: Pass 1 repiping finished. commit | commitdiff | tree | snapshot
2010-03-11 Joshua Wisetests/Makefile: Build without THUMB support. This... commit | commitdiff | tree | snapshot
2010-03-10 Joshua WiseGlobal: More re-piping, and a bugfix for a bug recently... commit | commitdiff | tree | snapshot
2010-03-10 Joshua Wisetests/Makefile: Build the testbench by default with... commit | commitdiff | tree | snapshot
2010-03-09 Joshua WiseIssue: AUTORESET. commit | commitdiff | tree | snapshot
2010-03-09 Joshua WiseIssue: Fix pipe names. commit | commitdiff | tree | snapshot
2010-02-27 Joshua WiseRegfile: Rename signals for correct pipe stages. commit | commitdiff | tree | snapshot
2010-02-22 Joshua WiseICache: Change cache_data to block RAM (yay!). commit | commitdiff | tree | snapshot
2010-02-22 Joshua WiseICache, Fetch: Re-pipe things such that the icache... commit | commitdiff | tree | snapshot
...
heads
13 years ago master shortlog | log | tree
13 years ago msater shortlog | log | tree
FireARM pipelined ARM-like CPU implementation in Verilog
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