memory: ldm/stm ready for testing, hopefully
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
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6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
14
15 /* regfile interface */
16 output reg [3:0] st_read,
17 input [31:0] st_data,
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18
19 /* stage inputs */
20 input inbubble,
21 input [31:0] pc,
22 input [31:0] insn,
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23 input [31:0] op0,
24 input [31:0] op1,
6d0f9d82 25 input [31:0] op2,
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26 input write_reg,
27 input [3:0] write_num,
28 input [31:0] write_data,
b3bb2fb8 29
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30 /* outputs */
31 output reg outstall,
32 output reg outbubble,
b3bb2fb8 33 output reg [31:0] outpc,
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34 output reg [31:0] outinsn,
35 output reg out_write_reg = 1'b0,
36 output reg [3:0] out_write_num = 4'bxxxx,
37 output reg [31:0] out_write_data = 32'hxxxxxxxx
38 );
b3bb2fb8 39
b114e03f 40 reg [31:0] addr, raddr, prev_raddr, next_regdata;
e08b748a 41 reg [3:0] next_regsel, cur_reg, prev_reg;
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42 reg next_writeback, next_notdone, next_inc_next;
43 reg [31:0] align_s1, align_s2, align_rddata;
e08b748a 44
c65110a8 45 wire next_outbubble;
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46 wire next_write_reg;
47 wire [3:0] next_write_num;
48 wire [31:0] next_write_data;
74d3729c 49
b783a475 50 reg [15:0] regs, next_regs;
e08b748a 51 reg started = 1'b0, next_started;
b114e03f 52 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 53
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54 reg notdone = 1'b0;
55 reg inc_next = 1'b0;
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56
57 always @(posedge clk)
58 begin
59 outpc <= pc;
60 outinsn <= insn;
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61 outbubble <= next_outbubble;
62 out_write_reg <= next_write_reg;
63 out_write_num <= next_write_num;
64 out_write_data <= next_write_data;
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65 notdone <= next_notdone;
66 inc_next <= next_inc_next;
e68b2378 67 regs <= next_regs;
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68 prev_reg <= cur_reg;
69 started <= next_started;
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70 prev_offset <= offset;
71 prev_raddr <= raddr;
a02ca509 72 end
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73
74 always @(*)
75 begin
76 addr = 32'hxxxxxxxx;
77 raddr = 32'hxxxxxxxx;
78 rd_req = 1'b0;
79 wr_req = 1'b0;
80 wr_data = 32'hxxxxxxxx;
81 busaddr = 32'hxxxxxxxx;
82 outstall = 1'b0;
74d3729c 83 next_notdone = 1'b0;
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84 next_write_reg = write_reg;
85 next_write_num = write_num;
86 next_write_data = write_data;
74d3729c 87 next_inc_next = 1'b0;
c65110a8 88 next_outbubble = inbubble;
a02ca509 89 outstall = 1'b0;
9f082c0b 90 next_regs = 16'b0;
e08b748a 91 next_started = started;
b114e03f 92 offset = prev_offset;
9f082c0b 93
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94 casez(insn)
95 `DECODE_LDRSTR_UNDEFINED: begin end
96 `DECODE_LDRSTR: begin
a02ca509 97 if (!inbubble) begin
c65110a8 98 next_outbubble = rw_wait;
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99 outstall = rw_wait | notdone;
100
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101 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
102 raddr = insn[24] ? op0 : addr; /* pre/post increment */
103 busaddr = {raddr[31:2], 2'b0};
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104 rd_req = insn[20];
105 wr_req = ~insn[20];
106
107 /* rotate to correct position */
108 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
109 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
110 /* select byte or word */
111 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
112
113 if(!insn[20]) begin
6d0f9d82 114 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
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115 end
116 else if(!inc_next) begin
117 next_write_reg = 1'b1;
118 next_write_num = insn[15:12];
119 next_write_data = align_rddata;
120 next_inc_next = 1'b1;
121 end
122 else if(insn[21]) begin
123 next_write_reg = 1'b1;
124 next_write_num = insn[19:16];
125 next_write_data = addr;
126 end
127 next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8 128 end
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129 end
130 `DECODE_LDMSTM: begin
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131 rd_req = insn[20];
132 wr_req = ~insn[20];
e08b748a 133 if(!started) begin
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134// next_regs = insn[23] ? op1[15:0] : op1[0:15];
135 /** verilator can suck my dick */
136 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
137 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
138 offset = 6'b0;
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139 next_started = 1'b1;
140 end
141 else if(inc_next) begin
142 if(insn[21]) begin
143 next_write_reg = 1'b1;
144 next_write_num = insn[19:16];
b114e03f 145 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
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146 end
147 next_started = 1'b0;
b783a475 148 end
e08b748a 149 else if(rw_wait) begin
9f082c0b 150 next_regs = regs;
e08b748a 151 cur_reg = prev_reg;
b114e03f 152 raddr = prev_raddr;
e08b748a 153 end
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154 else begin
155 casez(regs)
156 16'b???????????????1: begin
e08b748a 157 cur_reg = 4'h0;
b114e03f 158 next_regs = {regs[15:1], 1'b0};
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159 end
160 16'b??????????????10: begin
e08b748a 161 cur_reg = 4'h1;
b114e03f 162 next_regs = {regs[15:2], 2'b0};
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163 end
164 16'b?????????????100: begin
e08b748a 165 cur_reg = 4'h2;
b114e03f 166 next_regs = {regs[15:3], 3'b0};
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167 end
168 16'b????????????1000: begin
e08b748a 169 cur_reg = 4'h3;
b114e03f 170 next_regs = {regs[15:4], 4'b0};
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171 end
172 16'b???????????10000: begin
e08b748a 173 cur_reg = 4'h4;
b114e03f 174 next_regs = {regs[15:5], 5'b0};
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175 end
176 16'b??????????100000: begin
e08b748a 177 cur_reg = 4'h5;
b114e03f 178 next_regs = {regs[15:6], 6'b0};
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179 end
180 16'b?????????1000000: begin
e08b748a 181 cur_reg = 4'h6;
b114e03f 182 next_regs = {regs[15:7], 7'b0};
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183 end
184 16'b????????10000000: begin
e08b748a 185 cur_reg = 4'h7;
b114e03f 186 next_regs = {regs[15:8], 8'b0};
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187 end
188 16'b???????100000000: begin
e08b748a 189 cur_reg = 4'h8;
b114e03f 190 next_regs = {regs[15:9], 9'b0};
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191 end
192 16'b??????1000000000: begin
e08b748a 193 cur_reg = 4'h9;
b114e03f 194 next_regs = {regs[15:10], 10'b0};
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195 end
196 16'b?????10000000000: begin
e08b748a 197 cur_reg = 4'hA;
b114e03f 198 next_regs = {regs[15:11], 11'b0};
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199 end
200 16'b????100000000000: begin
e08b748a 201 cur_reg = 4'hB;
b114e03f 202 next_regs = {regs[15:12], 12'b0};
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203 end
204 16'b???1000000000000: begin
e08b748a 205 cur_reg = 4'hC;
b114e03f 206 next_regs = {regs[15:13], 13'b0};
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207 end
208 16'b??10000000000000: begin
e08b748a 209 cur_reg = 4'hD;
b114e03f 210 next_regs = {regs[15:14], 14'b0};
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211 end
212 16'b?100000000000000: begin
e08b748a 213 cur_reg = 4'hE;
b114e03f 214 next_regs = {regs[15], 15'b0};
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215 end
216 16'b1000000000000000: begin
e08b748a 217 cur_reg = 4'hF;
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218 next_regs = 16'b0;
219 end
220 default: begin
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221 cur_reg = 4'hx;
222 next_regs = 16'b0;
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223 end
224 endcase
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225 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
226 offset = prev_offset + 6'h4;
227 offset_sel = insn[24] ? offset : prev_offset;
228 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
229
230 if(insn[20]) begin
231 next_write_reg = 1'b1;
232 next_write_num = cur_reg;
233 next_write_data = rd_data;
234 end
235
236 st_read = cur_reg;
237 wr_data = st_data;
238
9f082c0b 239 next_inc_next = next_regs == 16'b0;
e08b748a 240 next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]);
b114e03f 241 busaddr = {raddr[31:2], 2'b0};
b783a475 242 end
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243 end
244 default: begin end
245 endcase
246 end
b3bb2fb8 247endmodule
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