DCache/ICache: reg i -> integer i
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8 6
ab7ee9fc
JW
7 input flush,
8
b3bb2fb8
CL
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
9fc6c23c 16 output reg [2:0] data_size,
b3bb2fb8
CL
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
a02ca509 21
979f2bd7
JW
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
804dc0bc 26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
979f2bd7 29
a02ca509
JW
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
e68b2378
JW
34 input [31:0] op0,
35 input [31:0] op1,
6d0f9d82 36 input [31:0] op2,
efd1aa13
CL
37 input [31:0] spsr,
38 input [31:0] cpsr,
a02ca509
JW
39 input write_reg,
40 input [3:0] write_num,
41 input [31:0] write_data,
b3bb2fb8 42
a02ca509
JW
43 /* outputs */
44 output reg outstall,
45 output reg outbubble,
b3bb2fb8 46 output reg [31:0] outpc,
a02ca509
JW
47 output reg [31:0] outinsn,
48 output reg out_write_reg = 1'b0,
49 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 50 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc
JW
51 output reg [31:0] outspsr = 32'hxxxxxxxx,
52 output reg [31:0] outcpsr = 32'hxxxxxxxx
a02ca509 53 );
b3bb2fb8 54
efd1aa13 55 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
666ceb03 56 reg [31:0] prevaddr;
e08b748a 57 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 58 reg next_writeback;
e08b748a 59
804dc0bc
JW
60 reg next_outbubble;
61 reg next_write_reg;
62 reg [3:0] next_write_num;
63 reg [31:0] next_write_data;
74d3729c 64
4d7253f1 65 reg [2:0] lsr_state = 3'b001, next_lsr_state;
666ceb03
CL
66 reg [31:0] align_s1, align_s2, align_rddata;
67
4d7253f1 68 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03
CL
69 reg [31:0] lsrh_rddata;
70 reg [15:0] lsrh_rddata_s1;
71 reg [7:0] lsrh_rddata_s2;
9a0d0e43 72
b783a475 73 reg [15:0] regs, next_regs;
4d7253f1 74 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 75 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 76
9a0d0e43
CL
77 reg [31:0] swp_oldval, next_swp_oldval;
78 reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509
JW
79
80 always @(posedge clk)
81 begin
82 outpc <= pc;
83 outinsn <= insn;
c65110a8
JW
84 outbubble <= next_outbubble;
85 out_write_reg <= next_write_reg;
86 out_write_num <= next_write_num;
87 out_write_data <= next_write_data;
e68b2378 88 regs <= next_regs;
e08b748a 89 prev_reg <= cur_reg;
95704fd3
JW
90 if (!rw_wait)
91 prev_offset <= offset;
b114e03f 92 prev_raddr <= raddr;
ab7ee9fc
JW
93 outcpsr <= next_outcpsr;
94 outspsr <= spsr;
9a0d0e43 95 swp_state <= next_swp_state;
666ceb03
CL
96 lsm_state <= next_lsm_state;
97 lsr_state <= next_lsr_state;
98 lsrh_state <= next_lsrh_state;
99 prevaddr <= addr;
a02ca509 100 end
d73619a2
JW
101
102 reg delayedflush = 0;
103 always @(posedge clk)
104 if (flush && outstall /* halp! I can't do it now, maybe later? */)
105 delayedflush <= 1;
106 else if (!outstall /* anything has been handled this time around */)
107 delayedflush <= 0;
b3bb2fb8
CL
108
109 always @(*)
110 begin
666ceb03 111 addr = prevaddr;
b3bb2fb8
CL
112 raddr = 32'hxxxxxxxx;
113 rd_req = 1'b0;
114 wr_req = 1'b0;
115 wr_data = 32'hxxxxxxxx;
116 busaddr = 32'hxxxxxxxx;
2bcc55d5 117 data_size = 3'bxxx;
b3bb2fb8 118 outstall = 1'b0;
a02ca509
JW
119 next_write_reg = write_reg;
120 next_write_num = write_num;
121 next_write_data = write_data;
c65110a8 122 next_outbubble = inbubble;
9a0d0e43 123 next_regs = regs;
979f2bd7 124 cp_req = 1'b0;
43e4332c
JW
125 cp_rnw = 1'bx;
126 cp_write = 32'hxxxxxxxx;
b114e03f 127 offset = prev_offset;
4d7253f1 128 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
666ceb03 129 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
130 lsrh_rddata_s1 = 16'hxxxx;
131 lsrh_rddata_s2 = 8'hxx;
9a0d0e43
CL
132 next_lsm_state = lsm_state;
133 next_lsr_state = lsr_state;
666ceb03 134 next_lsrh_state = lsrh_state;
9a0d0e43
CL
135 next_swp_oldval = swp_oldval;
136 next_swp_state = swp_state;
137 cur_reg = prev_reg;
9f082c0b 138
5989b2f5 139 /* XXX shit not given about endianness */
d73619a2 140 casez(insn)
5989b2f5
CL
141 `DECODE_ALU_SWP: if(!inbubble) begin
142 outstall = rw_wait;
143 next_outbubble = rw_wait;
144 busaddr = {op0[31:2], 2'b0};
2bcc55d5 145 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5
CL
146 case(swp_state)
147 2'b01: begin
148 rd_req = 1'b1;
149 outstall = 1'b1;
150 if(!rw_wait) begin
151 next_swp_state = 2'b10;
152 next_swp_oldval = rd_data;
9a0d0e43 153 end
fb529aac 154 $display("SWP: read stage");
9a0d0e43 155 end
5989b2f5
CL
156 2'b10: begin
157 wr_req = 1'b1;
2bcc55d5 158 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
159 next_write_reg = 1'b1;
160 next_write_num = insn[15:12];
2bcc55d5 161 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5
CL
162 if(!rw_wait)
163 next_swp_state = 2'b01;
fb529aac 164 $display("SWP: write stage");
5989b2f5
CL
165 end
166 default: begin end
167 endcase
9a0d0e43 168 end
fb529aac 169 `DECODE_ALU_MULT: begin end
666ceb03
CL
170 `DECODE_ALU_HDATA_REG,
171 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
172 next_outbubble = rw_wait;
173 outstall = rw_wait;
174 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
175 raddr = insn[24] ? op0 : addr; /* pre/post increment */
176 busaddr = raddr;
177 /* rotate to correct position */
178 case(insn[6:5])
179 2'b00: begin end /* swp */
180 2'b01: begin /* unsigned half */
181 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 182 data_size = 3'b010;
666ceb03
CL
183 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
184 end
185 2'b10: begin /* signed byte */
186 wr_data = {4{op2[7:0]}};
2bcc55d5 187 data_size = 3'b001;
666ceb03
CL
188 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
189 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
190 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
191 end
192 2'b11: begin /* signed half */
193 wr_data = {2{op2[15:0]}};
2bcc55d5 194 data_size = 3'b010;
666ceb03
CL
195 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
196 end
197 endcase
198
199 case(lsrh_state)
4d7253f1 200 3'b001: begin
666ceb03
CL
201 rd_req = insn[20];
202 wr_req = ~insn[20];
203 next_write_num = insn[15:12];
204 next_write_data = lsrh_rddata;
205 if(insn[20]) begin
206 next_write_reg = 1'b1;
207 end
d64d6ef9 208 if(insn[21] | !insn[24]) begin
666ceb03
CL
209 outstall = 1'b1;
210 if(!rw_wait)
4d7253f1 211 next_lsrh_state = 3'b010;
666ceb03 212 end
fb529aac 213 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
666ceb03 214 end
4d7253f1
JW
215 3'b010: begin
216 next_outbubble = 1'b0;
666ceb03
CL
217 next_write_reg = 1'b1;
218 next_write_num = insn[19:16];
219 next_write_data = addr;
4d7253f1
JW
220 next_lsrh_state = 3'b100;
221 end
222 3'b100: begin
223 outstall = 0;
224 next_lsrh_state = 3'b001;
666ceb03
CL
225 end
226 default: begin end
227 endcase
d64d6ef9
JW
228
229 if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
230 outstall = 1'b0;
231 next_lsrh_state = 3'b001;
232 end
666ceb03 233 end
b3bb2fb8 234 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
235 `DECODE_LDRSTR: if(!inbubble) begin
236 next_outbubble = rw_wait;
237 outstall = rw_wait;
238 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 239 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
240 busaddr = raddr;
241 /* rotate to correct position */
5989b2f5
CL
242 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
243 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
244 /* select byte or word */
245 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03 246 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
2bcc55d5 247 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 248 case(lsr_state)
4d7253f1 249 3'b001: begin
fb529aac
JW
250 rd_req = insn[20] /* L */;
251 wr_req = ~insn[20] /* L */;
252 next_write_reg = insn[20] /* L */;
666ceb03 253 next_write_num = insn[15:12];
fb529aac 254 if(insn[20] /* L */) begin
5989b2f5 255 next_write_data = align_rddata;
a02ca509 256 end
d64d6ef9 257 if(insn[21] /* W */ | !insn[24] /* P */) begin
5989b2f5
CL
258 outstall = 1'b1;
259 if(!rw_wait)
4d7253f1 260 next_lsr_state = 3'b010;
a02ca509 261 end
d73619a2 262 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8 263 end
4d7253f1
JW
264 3'b010: begin
265 outstall = 1;
266 next_outbubble = 0;
5989b2f5
CL
267 next_write_reg = 1'b1;
268 next_write_num = insn[19:16];
269 next_write_data = addr;
4d7253f1
JW
270 next_lsr_state = 3'b100;
271 end
272 3'b100: begin
273 outstall = 0;
274 next_lsr_state = 3'b001;
5989b2f5
CL
275 end
276 default: begin end
277 endcase
d64d6ef9
JW
278
279 if ((lsr_state == 3'b001) && flush) begin /* Reject it. */
280 outstall = 1'b0;
281 next_lsr_state = 3'b001;
282 end
b3bb2fb8 283 end
5989b2f5
CL
284 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
285 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43
CL
286 outstall = rw_wait;
287 next_outbubble = rw_wait;
2bcc55d5 288 data_size = 3'b100;
9a0d0e43 289 case(lsm_state)
4d7253f1 290 4'b0001: begin
b114e03f
CL
291// next_regs = insn[23] ? op1[15:0] : op1[0:15];
292 /** verilator can suck my dick */
b957d34d
JW
293 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
294 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
295 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 296 offset = 6'b0;
d64d6ef9
JW
297 outstall = 1'b1;
298 next_lsm_state = 4'b0010;
e08b748a 299 end
4d7253f1 300 4'b0010: begin
9a0d0e43
CL
301 rd_req = insn[20];
302 wr_req = ~insn[20];
9f082c0b
CL
303 casez(regs)
304 16'b???????????????1: begin
e08b748a 305 cur_reg = 4'h0;
b114e03f 306 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
307 end
308 16'b??????????????10: begin
e08b748a 309 cur_reg = 4'h1;
b114e03f 310 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
311 end
312 16'b?????????????100: begin
e08b748a 313 cur_reg = 4'h2;
b114e03f 314 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
315 end
316 16'b????????????1000: begin
e08b748a 317 cur_reg = 4'h3;
b114e03f 318 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
319 end
320 16'b???????????10000: begin
e08b748a 321 cur_reg = 4'h4;
b114e03f 322 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
323 end
324 16'b??????????100000: begin
e08b748a 325 cur_reg = 4'h5;
b114e03f 326 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
327 end
328 16'b?????????1000000: begin
e08b748a 329 cur_reg = 4'h6;
b114e03f 330 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
331 end
332 16'b????????10000000: begin
e08b748a 333 cur_reg = 4'h7;
b114e03f 334 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
335 end
336 16'b???????100000000: begin
e08b748a 337 cur_reg = 4'h8;
b114e03f 338 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
339 end
340 16'b??????1000000000: begin
e08b748a 341 cur_reg = 4'h9;
b114e03f 342 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
343 end
344 16'b?????10000000000: begin
e08b748a 345 cur_reg = 4'hA;
b114e03f 346 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
347 end
348 16'b????100000000000: begin
e08b748a 349 cur_reg = 4'hB;
b114e03f 350 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
351 end
352 16'b???1000000000000: begin
e08b748a 353 cur_reg = 4'hC;
b114e03f 354 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
355 end
356 16'b??10000000000000: begin
e08b748a 357 cur_reg = 4'hD;
b114e03f 358 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
359 end
360 16'b?100000000000000: begin
e08b748a 361 cur_reg = 4'hE;
b114e03f 362 next_regs = {regs[15], 15'b0};
9f082c0b
CL
363 end
364 16'b1000000000000000: begin
e08b748a 365 cur_reg = 4'hF;
9f082c0b
CL
366 next_regs = 16'b0;
367 end
368 default: begin
e08b748a
CL
369 cur_reg = 4'hx;
370 next_regs = 16'b0;
9f082c0b
CL
371 end
372 endcase
b957d34d 373 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13
CL
374 if(cur_reg == 4'hF && insn[22]) begin
375 next_outcpsr = spsr;
376 end
b114e03f 377
95704fd3 378 offset = prev_offset + 6'h4;
d73619a2
JW
379 offset_sel = insn[24] ? offset : prev_offset;
380 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
381 if(insn[20]) begin
382 next_write_reg = !rw_wait;
383 next_write_num = cur_reg;
384 next_write_data = rd_data;
385 end
386 if (rw_wait) begin
387 next_regs = regs;
388 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
389 end
390
391 st_read = cur_reg;
b957d34d 392 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 393 busaddr = raddr;
b957d34d 394
d73619a2 395 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43
CL
396
397 outstall = 1'b1;
398
399 if(next_regs == 16'b0) begin
4d7253f1 400 next_lsm_state = 4'b0100;
9a0d0e43
CL
401 end
402 end
4d7253f1
JW
403 4'b0100: begin
404 outstall = 1;
405 next_outbubble = 0;
b957d34d 406 next_write_reg = insn[21] /* writeback */;
9a0d0e43
CL
407 next_write_num = insn[19:16];
408 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
4d7253f1 409 next_lsm_state = 4'b1000;
d73619a2 410 $display("LDMSTM: Stage 3: Writing back");
b783a475 411 end
4d7253f1
JW
412 4'b1000: begin
413 outstall = 0;
414 next_lsm_state = 4'b0001;
415 end
d73619a2 416 default: $stop;
9a0d0e43 417 endcase
d64d6ef9
JW
418 if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
419 outstall = 1'b0;
420 next_lsm_state = 4'b0001;
421 end
d73619a2 422 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8 423 end
5989b2f5 424 `DECODE_LDCSTC: if(!inbubble) begin
43e4332c
JW
425 $display("WARNING: Unimplemented LDCSTC");
426 end
5989b2f5 427 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
428 cp_req = 1;
429 if (cp_busy) begin
430 outstall = 1;
431 next_outbubble = 1;
432 end
433 if (!cp_ack) begin
434 /* XXX undefined instruction trap */
435 $display("WARNING: Possible CDP undefined instruction");
436 end
437 end
5989b2f5 438 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
439 cp_req = 1;
440 cp_rnw = insn[20] /* L */;
441 if (insn[20] == 0 /* store to coprocessor */)
442 cp_write = op0;
443 else begin
d1d0eb8e
JW
444 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
445 next_write_reg = 1'b1;
446 next_write_num = insn[15:12];
447 next_write_data = cp_read;
448 end else
449 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c
JW
450 end
451 if (cp_busy) begin
452 outstall = 1;
453 next_outbubble = 1;
454 end
455 if (!cp_ack) begin
838e283e 456 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 457 end
838e283e 458 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 459 end
b3bb2fb8
CL
460 default: begin end
461 endcase
d73619a2
JW
462
463 if ((flush || delayedflush) && !outstall)
464 next_outbubble = 1'b1;
b3bb2fb8 465 end
b3bb2fb8 466endmodule
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