st_data -> op2
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
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6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
14
15 /* regfile interface */
16 output reg [3:0] st_read,
17 input [31:0] st_data,
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18
19 /* stage inputs */
20 input inbubble,
21 input [31:0] pc,
22 input [31:0] insn,
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23 input [31:0] op0,
24 input [31:0] op1,
6d0f9d82 25 input [31:0] op2,
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26 input write_reg,
27 input [3:0] write_num,
28 input [31:0] write_data,
b3bb2fb8 29
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30 /* outputs */
31 output reg outstall,
32 output reg outbubble,
b3bb2fb8 33 output reg [31:0] outpc,
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34 output reg [31:0] outinsn,
35 output reg out_write_reg = 1'b0,
36 output reg [3:0] out_write_num = 4'bxxxx,
37 output reg [31:0] out_write_data = 32'hxxxxxxxx
38 );
b3bb2fb8 39
5bcb3b7e 40 reg [31:0] addr, raddr, next_regdata;
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41 reg [3:0] next_regsel;
42 reg next_writeback, next_notdone, next_inc_next;
43 reg [31:0] align_s1, align_s2, align_rddata;
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44
45 wire next_write_reg;
46 wire [3:0] next_write_num;
47 wire [31:0] next_write_data;
74d3729c 48
b783a475 49 reg [15:0] regs, next_regs;
74d3729c 50
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51 reg notdone = 1'b0;
52 reg inc_next = 1'b0;
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53
54 always @(posedge clk)
55 begin
56 outpc <= pc;
57 outinsn <= insn;
58 outbubble <= rw_wait;
59 out_write_reg <= next_writeback;
60 out_write_num <= next_regsel;
61 out_write_data <= next_regdata;
62 notdone <= next_notdone;
63 inc_next <= next_inc_next;
e68b2378 64 regs <= next_regs;
a02ca509 65 end
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66
67 always @(*)
68 begin
69 addr = 32'hxxxxxxxx;
70 raddr = 32'hxxxxxxxx;
71 rd_req = 1'b0;
72 wr_req = 1'b0;
73 wr_data = 32'hxxxxxxxx;
74 busaddr = 32'hxxxxxxxx;
75 outstall = 1'b0;
74d3729c 76 next_notdone = 1'b0;
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77 next_write_reg = write_reg;
78 next_write_num = write_num;
79 next_write_data = write_data;
74d3729c 80 next_inc_next = 1'b0;
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81 outstall = 1'b0;
82
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83 casez(insn)
84 `DECODE_LDRSTR_UNDEFINED: begin end
85 `DECODE_LDRSTR: begin
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86 if (!inbubble) begin
87 outstall = rw_wait | notdone;
88
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89 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
90 raddr = insn[24] ? op0 : addr; /* pre/post increment */
91 busaddr = {raddr[31:2], 2'b0};
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92 rd_req = insn[20];
93 wr_req = ~insn[20];
94
95 /* rotate to correct position */
96 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
97 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
98 /* select byte or word */
99 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
100
101 if(!insn[20]) begin
6d0f9d82 102 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
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103 end
104 else if(!inc_next) begin
105 next_write_reg = 1'b1;
106 next_write_num = insn[15:12];
107 next_write_data = align_rddata;
108 next_inc_next = 1'b1;
109 end
110 else if(insn[21]) begin
111 next_write_reg = 1'b1;
112 next_write_num = insn[19:16];
113 next_write_data = addr;
114 end
115 next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8 116 end
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117 end
118 `DECODE_LDMSTM: begin
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119 busaddr = {op0[31:2], 2'b0};
120 rd_req = insn[20];
121 wr_req = ~insn[20];
122 casez(regs)
123 16'b???????????????1: begin
124 next_regs = regs;
125 end
126 16'b??????????????10: begin
127 end
128 16'b?????????????100: begin
129 end
130 16'b????????????1000: begin
131 end
132 16'b???????????10000: begin
133 end
134 16'b??????????100000: begin
135 end
136 16'b?????????1000000: begin
137 end
138 16'b????????10000000: begin
139 end
140 16'b???????100000000: begin
141 end
142 16'b??????1000000000: begin
143 end
144 16'b?????10000000000: begin
145 end
146 16'b????100000000000: begin
147 end
148 16'b???1000000000000: begin
149 end
150 16'b??10000000000000: begin
151 end
152 16'b?100000000000000: begin
153 end
154 16'b1000000000000000: begin
155 end
156 default: begin
157 next_inc_next = 1'b1;
158 end
159 endcase
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160 end
161 default: begin end
162 endcase
163 end
b3bb2fb8 164endmodule
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