Memory: Move coprocessor and register outputs to their own always blocks.
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
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3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
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21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
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25 input flush,
26
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27 /* bus interface */
28 output reg [31:0] busaddr,
29 output reg rd_req,
30 output reg wr_req,
31 input rw_wait,
32 output reg [31:0] wr_data,
33 input [31:0] rd_data,
9fc6c23c 34 output reg [2:0] data_size,
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35
36 /* regfile interface */
37 output reg [3:0] st_read,
38 input [31:0] st_data,
a02ca509 39
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40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
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45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
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48 /* stage inputs */
49 input inbubble,
50 input [31:0] pc,
51 input [31:0] insn,
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52 input [31:0] op0,
53 input [31:0] op1,
6d0f9d82 54 input [31:0] op2,
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55 input [31:0] spsr,
56 input [31:0] cpsr,
fdecc897 57 input cpsrup,
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58 input write_reg,
59 input [3:0] write_num,
60 input [31:0] write_data,
b3bb2fb8 61
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62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
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66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
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71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
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81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
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87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
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90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
9a0d0e43
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98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
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100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
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103
104 always @(posedge clk)
105 begin
106 outpc <= pc;
107 outinsn <= insn;
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108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
e68b2378 112 regs <= next_regs;
e08b748a 113 prev_reg <= cur_reg;
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114 if (!rw_wait)
115 prev_offset <= offset;
b114e03f 116 prev_raddr <= raddr;
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117 outcpsr <= next_outcpsr;
118 outspsr <= spsr;
fdecc897 119 outcpsrup <= next_outcpsrup;
9a0d0e43 120 swp_state <= next_swp_state;
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121 lsm_state <= next_lsm_state;
122 lsr_state <= next_lsr_state;
123 lsrh_state <= next_lsrh_state;
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124 if (do_rd_data_latch)
125 rd_data_latch <= rd_data;
666ceb03 126 prevaddr <= addr;
a02ca509 127 end
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128
129 reg delayedflush = 0;
130 always @(posedge clk)
131 if (flush && outstall /* halp! I can't do it now, maybe later? */)
132 delayedflush <= 1;
133 else if (!outstall /* anything has been handled this time around */)
134 delayedflush <= 0;
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135
136 /* Drive the state machines and stall. */
137 always @(*)
138 begin
139 outstall = 1'b0;
140 next_lsm_state = lsm_state;
141 next_lsr_state = lsr_state;
142 next_lsrh_state = lsrh_state;
143 next_swp_state = swp_state;
144 casez(insn)
145 `DECODE_ALU_SWP: if(!inbubble) begin
146 case(swp_state)
147 `SWP_READING: begin
148 outstall = 1'b1;
149 if (!rw_wait)
150 next_swp_state = `SWP_WRITING;
151 $display("SWP: read stage");
152 end
153 `SWP_WRITING: begin
154 outstall = rw_wait;
155 if(!rw_wait)
156 next_swp_state = `SWP_READING;
157 $display("SWP: write stage");
158 end
159 default: begin
160 outstall = 1'bx;
161 next_swp_state = 2'bxx;
162 end
163 endcase
164 end
165 `DECODE_ALU_MULT: begin end
166 `DECODE_ALU_HDATA_REG,
167 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
168 case(lsrh_state)
169 `LSRH_MEMIO: begin
170 outstall = rw_wait;
171 if(insn[21] | !insn[24]) begin
172 outstall = 1'b1;
173 if(!rw_wait)
174 next_lsrh_state = `LSRH_BASEWB;
175 end
176
177 if (flush) /* special case! */ begin
178 outstall = 1'b0;
179 next_lsrh_state = `LSRH_MEMIO;
180 end
181
182 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
183 end
184 `LSRH_BASEWB: begin
185 outstall = 1'b1;
186 next_lsrh_state = `LSRH_WBFLUSH;
187 end
188 `LSRH_WBFLUSH: begin
189 outstall = 1'b0;
190 next_lsrh_state = `LSRH_MEMIO;
191 end
192 default: begin
193 outstall = 1'bx;
194 next_lsrh_state = 3'bxxx;
195 end
196 endcase
197 end
198 `DECODE_LDRSTR_UNDEFINED: begin end
199 `DECODE_LDRSTR: if(!inbubble) begin
200 outstall = rw_wait;
201 case(lsr_state)
202 `LSR_MEMIO: begin
203 outstall = rw_wait;
204 next_lsr_state = `LSR_MEMIO;
205 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
206 outstall = 1'b1;
207 if (!rw_wait)
208 next_lsr_state = `LSR_STRB_WR;
209 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
210 outstall = 1'b1;
211 if (!rw_wait)
212 next_lsr_state = `LSR_BASEWB;
213 end
214
215 if (flush) begin
216 outstall = 1'b0;
217 next_lsr_state = `LSR_MEMIO;
218 end
219 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
220 end
221 `LSR_STRB_WR: begin
222 outstall = 1;
223 if(insn[21] /* W */ | !insn[24] /* P */) begin
224 if(!rw_wait)
225 next_lsr_state = `LSR_BASEWB;
226 end else if (!rw_wait)
227 next_lsr_state = `LSR_WBFLUSH;
228 $display("LDRSTR: Handling STRB");
229 end
230 `LSR_BASEWB: begin
231 outstall = 1;
232 next_lsr_state = `LSR_WBFLUSH;
233 end
234 `LSR_WBFLUSH: begin
235 outstall = 0;
236 next_lsr_state = `LSR_MEMIO;
237 end
238 default: begin
239 outstall = 1'bx;
240 next_lsr_state = 4'bxxxx;
241 end
242 endcase
243 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
244 end
245 `DECODE_LDMSTM: if(!inbubble) begin
246 outstall = rw_wait;
247 case(lsm_state)
248 `LSM_SETUP: begin
249 outstall = 1'b1;
250 next_lsm_state = `LSM_MEMIO;
251 if (flush) begin
252 outstall = 1'b0;
253 next_lsm_state = `LSM_SETUP;
254 end
255 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
256 end
257 `LSM_MEMIO: begin
258 outstall = 1'b1;
259 if(next_regs == 16'b0) begin
260 next_lsm_state = `LSM_BASEWB;
261 end
262
263 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
264 end
265 `LSM_BASEWB: begin
266 outstall = 1;
267 next_lsm_state = `LSM_WBFLUSH;
268 $display("LDMSTM: Stage 3: Writing back");
269 end
270 `LSM_WBFLUSH: begin
271 outstall = 0;
272 next_lsm_state = `LSM_SETUP;
273 end
274 default: begin
275 outstall = 1'bx;
276 next_lsm_state = 4'bxxxx;
277 end
278 endcase
279 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
280 end
281 `DECODE_LDCSTC: if(!inbubble) begin
282 $display("WARNING: Unimplemented LDCSTC");
283 end
284 `DECODE_CDP: if (!inbubble) begin
285 if (cp_busy) begin
286 outstall = 1;
287 end
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288 if (!cp_ack) begin
289 /* XXX undefined instruction trap */
290 $display("WARNING: Possible CDP undefined instruction");
291 end
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292 end
293 `DECODE_MRCMCR: if (!inbubble) begin
294 if (cp_busy) begin
295 outstall = 1;
296 end
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297 if (!cp_ack) begin
298 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
299 end
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300 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
301 end
302 default: begin end
303 endcase
304 end
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305
306 /* Coprocessor input. */
307 always @(*)
308 begin
309 cp_req = 0;
310 cp_rnw = 1'bx;
311 cp_write = 32'hxxxxxxxx;
312 casez (insn)
313 `DECODE_CDP: if(!inbubble) begin
314 cp_req = 1;
315 end
316 `DECODE_MRCMCR: if(!inbubble) begin
317 cp_req = 1;
318 cp_rnw = insn[20] /* L */;
319 if (insn[20] == 0 /* store to coprocessor */)
320 cp_write = op0;
321 end
322 endcase
323 end
324
325 /* Register output logic. */
326
327 always @(*)
328 begin
329 next_write_reg = write_reg;
330 next_write_num = write_num;
331 next_write_data = write_data;
332 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
333 next_outcpsrup = cpsrup;
334
335 casez(insn)
336 `DECODE_ALU_SWP: if (!inbubble) begin
337 next_write_reg = 1'bx;
338 next_write_num = 4'bxxxx;
339 next_write_data = 32'hxxxxxxxx;
340 case(swp_state)
341 `SWP_READING:
342 next_write_reg = 1'b0;
343 `SWP_WRITING: begin
344 next_write_reg = 1'b1;
345 next_write_num = insn[15:12];
346 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
347 end
348 default: begin end
349 endcase
350 end
351 `DECODE_ALU_MULT: begin end
352 `DECODE_ALU_HDATA_REG,
353 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
354 next_write_reg = 1'bx;
355 next_write_num = 4'bxxxx;
356 next_write_data = 32'hxxxxxxxx;
357 case(lsrh_state)
358 `LSRH_MEMIO: begin
359 next_write_num = insn[15:12];
360 next_write_data = lsrh_rddata;
361 if(insn[20]) begin
362 next_write_reg = 1'b1;
363 end
364 end
365 `LSRH_BASEWB: begin
366 next_write_reg = 1'b1;
367 next_write_num = insn[19:16];
368 next_write_data = addr;
369 end
370 `LSRH_WBFLUSH:
371 next_write_reg = 1'b0;
372 default: begin end
373 endcase
374 end
375 `DECODE_LDRSTR_UNDEFINED: begin end
376 `DECODE_LDRSTR: if(!inbubble) begin
377 next_write_reg = 1'bx;
378 next_write_num = 4'bxxxx;
379 next_write_data = 32'hxxxxxxxx;
380 case(lsr_state)
381 `LSR_MEMIO: begin
382 next_write_reg = insn[20] /* L */;
383 next_write_num = insn[15:12];
384 if(insn[20] /* L */) begin
385 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
386 end
387 end
388 `LSR_STRB_WR:
389 next_write_reg = 1'b0;
390 `LSR_BASEWB: begin
391 next_write_reg = 1'b1;
392 next_write_num = insn[19:16];
393 next_write_data = addr;
394 end
395 `LSR_WBFLUSH:
396 next_write_reg = 1'b0;
397 default: begin end
398 endcase
399 end
400 `DECODE_LDMSTM: if(!inbubble) begin
401 next_write_reg = 1'bx;
402 next_write_num = 4'bxxxx;
403 next_write_data = 32'hxxxxxxxx;
404 case(lsm_state)
405 `LSM_SETUP:
406 next_write_reg = 1'b0;
407 `LSM_MEMIO: begin
408 if(insn[20]) begin
409 next_write_reg = !rw_wait;
410 next_write_num = cur_reg;
411 next_write_data = rd_data;
412 end else
413 next_write_reg = 1'b0;
414 end
415 `LSM_BASEWB: begin
416 next_write_reg = insn[21] /* writeback */;
417 next_write_num = insn[19:16];
418 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
419 if(cur_reg == 4'hF && insn[22]) begin
420 next_outcpsr = spsr;
421 next_outcpsrup = 1;
422 end
423 end
424 `LSM_WBFLUSH:
425 next_write_reg = 1'b0;
426 default: begin end
427 endcase
428 end
429 `DECODE_MRCMCR: if(!inbubble) begin
430 next_write_reg = 1'bx;
431 next_write_num = 4'bxxxx;
432 next_write_data = 32'hxxxxxxxx;
433 next_outcpsr = 32'hxxxxxxxx;
434 next_outcpsrup = 1'bx;
435 if (insn[20] == 1 /* load from coprocessor */)
436 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
437 next_write_reg = 1'b1;
438 next_write_num = insn[15:12];
439 next_write_data = cp_read;
440 end else begin
441 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
442 next_outcpsrup = 1;
443 end
444 end
445 endcase
446 end
447
b3bb2fb8
CL
448 always @(*)
449 begin
666ceb03 450 addr = prevaddr;
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CL
451 raddr = 32'hxxxxxxxx;
452 rd_req = 1'b0;
453 wr_req = 1'b0;
454 wr_data = 32'hxxxxxxxx;
455 busaddr = 32'hxxxxxxxx;
2bcc55d5 456 data_size = 3'bxxx;
cc1ce5b3 457 st_read = 4'hx;
6d18bf27 458 do_rd_data_latch = 0;
1ce42ada 459
c65110a8 460 next_outbubble = inbubble;
9a0d0e43 461 next_regs = regs;
1ce42ada 462
b114e03f 463 offset = prev_offset;
666ceb03 464 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
465 lsrh_rddata_s1 = 16'hxxxx;
466 lsrh_rddata_s2 = 8'hxx;
9a0d0e43 467 next_swp_oldval = swp_oldval;
9a0d0e43 468 cur_reg = prev_reg;
9f082c0b 469
5989b2f5 470 /* XXX shit not given about endianness */
d73619a2 471 casez(insn)
5989b2f5 472 `DECODE_ALU_SWP: if(!inbubble) begin
5989b2f5
CL
473 next_outbubble = rw_wait;
474 busaddr = {op0[31:2], 2'b0};
2bcc55d5 475 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 476 case(swp_state)
ab12fa63 477 `SWP_READING: begin
5989b2f5 478 rd_req = 1'b1;
5989b2f5 479 if(!rw_wait) begin
5989b2f5 480 next_swp_oldval = rd_data;
9a0d0e43 481 end
9a0d0e43 482 end
ab12fa63 483 `SWP_WRITING: begin
5989b2f5 484 wr_req = 1'b1;
2bcc55d5 485 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
486 end
487 default: begin end
488 endcase
9a0d0e43 489 end
fb529aac 490 `DECODE_ALU_MULT: begin end
666ceb03
CL
491 `DECODE_ALU_HDATA_REG,
492 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
493 next_outbubble = rw_wait;
666ceb03
CL
494 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
495 raddr = insn[24] ? op0 : addr; /* pre/post increment */
496 busaddr = raddr;
497 /* rotate to correct position */
498 case(insn[6:5])
666ceb03
CL
499 2'b01: begin /* unsigned half */
500 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 501 data_size = 3'b010;
666ceb03
CL
502 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
503 end
504 2'b10: begin /* signed byte */
505 wr_data = {4{op2[7:0]}};
2bcc55d5 506 data_size = 3'b001;
666ceb03
CL
507 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
508 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
509 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
510 end
511 2'b11: begin /* signed half */
512 wr_data = {2{op2[15:0]}};
2bcc55d5 513 data_size = 3'b010;
666ceb03
CL
514 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
515 end
ab12fa63
JW
516 default: begin
517 wr_data = 32'hxxxxxxxx;
518 data_size = 3'bxxx;
519 lsrh_rddata = 32'hxxxxxxxx;
520 end
666ceb03
CL
521 endcase
522
523 case(lsrh_state)
ab12fa63 524 `LSRH_MEMIO: begin
666ceb03
CL
525 rd_req = insn[20];
526 wr_req = ~insn[20];
666ceb03 527 end
1ce42ada 528 `LSRH_BASEWB:
4d7253f1 529 next_outbubble = 1'b0;
1ce42ada 530 `LSRH_WBFLUSH: begin end
666ceb03
CL
531 default: begin end
532 endcase
533 end
b3bb2fb8 534 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
535 `DECODE_LDRSTR: if(!inbubble) begin
536 next_outbubble = rw_wait;
5989b2f5 537 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 538 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
539 busaddr = raddr;
540 /* rotate to correct position */
5989b2f5
CL
541 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
542 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
543 /* select byte or word */
544 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
6d18bf27 545 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5 546 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 547 case(lsr_state)
ab12fa63 548 `LSR_MEMIO: begin
6d18bf27
JW
549 rd_req = insn[20] /* L */ || insn[22] /* B */;
550 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
6d18bf27
JW
551 if (insn[22] /* B */ && !insn[20] /* L */) begin
552 do_rd_data_latch = 1;
a02ca509 553 end
b3bb2fb8 554 end
ab12fa63 555 `LSR_STRB_WR: begin
6d18bf27
JW
556 rd_req = 0;
557 wr_req = 1;
558 next_write_reg = 0;
559 case (busaddr[1:0])
560 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
561 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
562 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
563 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
564 endcase
6d18bf27 565 end
ab12fa63 566 `LSR_BASEWB: begin
6d18bf27 567 rd_req = 0;
bb2595ed 568 wr_req = 0;
4d7253f1 569 next_outbubble = 0;
4d7253f1 570 end
ab12fa63 571 `LSR_WBFLUSH: begin
6d18bf27 572 rd_req = 0;
bb2595ed 573 wr_req = 0;
5989b2f5
CL
574 end
575 default: begin end
576 endcase
b3bb2fb8 577 end
5989b2f5
CL
578 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
579 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 580 next_outbubble = rw_wait;
2bcc55d5 581 data_size = 3'b100;
9a0d0e43 582 case(lsm_state)
ab12fa63 583 `LSM_SETUP: begin
b114e03f
CL
584// next_regs = insn[23] ? op1[15:0] : op1[0:15];
585 /** verilator can suck my dick */
b957d34d
JW
586 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
587 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 588 offset = 6'b0;
e08b748a 589 end
bb2595ed 590 `LSM_MEMIO: begin
9a0d0e43
CL
591 rd_req = insn[20];
592 wr_req = ~insn[20];
9f082c0b
CL
593 casez(regs)
594 16'b???????????????1: begin
e08b748a 595 cur_reg = 4'h0;
b114e03f 596 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
597 end
598 16'b??????????????10: begin
e08b748a 599 cur_reg = 4'h1;
b114e03f 600 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
601 end
602 16'b?????????????100: begin
e08b748a 603 cur_reg = 4'h2;
b114e03f 604 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
605 end
606 16'b????????????1000: begin
e08b748a 607 cur_reg = 4'h3;
b114e03f 608 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
609 end
610 16'b???????????10000: begin
e08b748a 611 cur_reg = 4'h4;
b114e03f 612 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
613 end
614 16'b??????????100000: begin
e08b748a 615 cur_reg = 4'h5;
b114e03f 616 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
617 end
618 16'b?????????1000000: begin
e08b748a 619 cur_reg = 4'h6;
b114e03f 620 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
621 end
622 16'b????????10000000: begin
e08b748a 623 cur_reg = 4'h7;
b114e03f 624 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
625 end
626 16'b???????100000000: begin
e08b748a 627 cur_reg = 4'h8;
b114e03f 628 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
629 end
630 16'b??????1000000000: begin
e08b748a 631 cur_reg = 4'h9;
b114e03f 632 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
633 end
634 16'b?????10000000000: begin
e08b748a 635 cur_reg = 4'hA;
b114e03f 636 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
637 end
638 16'b????100000000000: begin
e08b748a 639 cur_reg = 4'hB;
b114e03f 640 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
641 end
642 16'b???1000000000000: begin
e08b748a 643 cur_reg = 4'hC;
b114e03f 644 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
645 end
646 16'b??10000000000000: begin
e08b748a 647 cur_reg = 4'hD;
b114e03f 648 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
649 end
650 16'b?100000000000000: begin
e08b748a 651 cur_reg = 4'hE;
b114e03f 652 next_regs = {regs[15], 15'b0};
9f082c0b
CL
653 end
654 16'b1000000000000000: begin
e08b748a 655 cur_reg = 4'hF;
9f082c0b
CL
656 next_regs = 16'b0;
657 end
658 default: begin
e08b748a
CL
659 cur_reg = 4'hx;
660 next_regs = 16'b0;
9f082c0b
CL
661 end
662 endcase
b957d34d 663 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
b114e03f 664
95704fd3 665 offset = prev_offset + 6'h4;
d73619a2
JW
666 offset_sel = insn[24] ? offset : prev_offset;
667 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
d73619a2
JW
668 if (rw_wait) begin
669 next_regs = regs;
670 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
671 end
672
673 st_read = cur_reg;
b957d34d 674 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 675 busaddr = raddr;
9a0d0e43 676 end
1ce42ada 677 `LSM_BASEWB:
4d7253f1 678 next_outbubble = 0;
bb2595ed 679 `LSM_WBFLUSH: begin end
d73619a2 680 default: $stop;
9a0d0e43 681 endcase
43e4332c 682 end
bb2595ed 683 `DECODE_LDCSTC: begin end
5989b2f5 684 `DECODE_CDP: if(!inbubble) begin
43e4332c 685 if (cp_busy) begin
43e4332c
JW
686 next_outbubble = 1;
687 end
43e4332c 688 end
5989b2f5 689 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c 690 if (cp_busy) begin
43e4332c
JW
691 next_outbubble = 1;
692 end
43e4332c 693 end
b3bb2fb8
CL
694 default: begin end
695 endcase
d73619a2
JW
696
697 if ((flush || delayedflush) && !outstall)
698 next_outbubble = 1'b1;
b3bb2fb8 699 end
b3bb2fb8 700endmodule
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