Memory: Remove magic numbers from state machines.
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8 6
ab7ee9fc
JW
7 input flush,
8
b3bb2fb8
CL
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
9fc6c23c 16 output reg [2:0] data_size,
b3bb2fb8
CL
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
a02ca509 21
979f2bd7
JW
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
804dc0bc 26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
979f2bd7 29
a02ca509
JW
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
e68b2378
JW
34 input [31:0] op0,
35 input [31:0] op1,
6d0f9d82 36 input [31:0] op2,
efd1aa13
CL
37 input [31:0] spsr,
38 input [31:0] cpsr,
fdecc897 39 input cpsrup,
a02ca509
JW
40 input write_reg,
41 input [3:0] write_num,
42 input [31:0] write_data,
b3bb2fb8 43
a02ca509
JW
44 /* outputs */
45 output reg outstall,
46 output reg outbubble,
b3bb2fb8 47 output reg [31:0] outpc,
a02ca509
JW
48 output reg [31:0] outinsn,
49 output reg out_write_reg = 1'b0,
50 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 51 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 52 output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897
JW
53 output reg [31:0] outcpsr = 32'hxxxxxxxx,
54 output reg outcpsrup = 1'hx
a02ca509 55 );
b3bb2fb8 56
efd1aa13 57 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 58 reg next_outcpsrup;
666ceb03 59 reg [31:0] prevaddr;
e08b748a 60 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 61 reg next_writeback;
e08b748a 62
804dc0bc
JW
63 reg next_outbubble;
64 reg next_write_reg;
65 reg [3:0] next_write_num;
66 reg [31:0] next_write_data;
74d3729c 67
6d18bf27 68 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
666ceb03
CL
69 reg [31:0] align_s1, align_s2, align_rddata;
70
4d7253f1 71 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03
CL
72 reg [31:0] lsrh_rddata;
73 reg [15:0] lsrh_rddata_s1;
74 reg [7:0] lsrh_rddata_s2;
9a0d0e43 75
b783a475 76 reg [15:0] regs, next_regs;
4d7253f1 77 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 78 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 79
9a0d0e43
CL
80 reg [31:0] swp_oldval, next_swp_oldval;
81 reg [1:0] swp_state = 2'b01, next_swp_state;
6d18bf27
JW
82
83 reg do_rd_data_latch;
84 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
a02ca509
JW
85
86 always @(posedge clk)
87 begin
88 outpc <= pc;
89 outinsn <= insn;
c65110a8
JW
90 outbubble <= next_outbubble;
91 out_write_reg <= next_write_reg;
92 out_write_num <= next_write_num;
93 out_write_data <= next_write_data;
e68b2378 94 regs <= next_regs;
e08b748a 95 prev_reg <= cur_reg;
95704fd3
JW
96 if (!rw_wait)
97 prev_offset <= offset;
b114e03f 98 prev_raddr <= raddr;
ab7ee9fc
JW
99 outcpsr <= next_outcpsr;
100 outspsr <= spsr;
fdecc897 101 outcpsrup <= next_outcpsrup;
9a0d0e43 102 swp_state <= next_swp_state;
666ceb03
CL
103 lsm_state <= next_lsm_state;
104 lsr_state <= next_lsr_state;
105 lsrh_state <= next_lsrh_state;
6d18bf27
JW
106 if (do_rd_data_latch)
107 rd_data_latch <= rd_data;
666ceb03 108 prevaddr <= addr;
a02ca509 109 end
d73619a2
JW
110
111 reg delayedflush = 0;
112 always @(posedge clk)
113 if (flush && outstall /* halp! I can't do it now, maybe later? */)
114 delayedflush <= 1;
115 else if (!outstall /* anything has been handled this time around */)
116 delayedflush <= 0;
b3bb2fb8
CL
117
118 always @(*)
119 begin
666ceb03 120 addr = prevaddr;
b3bb2fb8
CL
121 raddr = 32'hxxxxxxxx;
122 rd_req = 1'b0;
123 wr_req = 1'b0;
124 wr_data = 32'hxxxxxxxx;
125 busaddr = 32'hxxxxxxxx;
2bcc55d5 126 data_size = 3'bxxx;
b3bb2fb8 127 outstall = 1'b0;
cc1ce5b3 128 st_read = 4'hx;
6d18bf27 129 do_rd_data_latch = 0;
a02ca509
JW
130 next_write_reg = write_reg;
131 next_write_num = write_num;
132 next_write_data = write_data;
c65110a8 133 next_outbubble = inbubble;
9a0d0e43 134 next_regs = regs;
979f2bd7 135 cp_req = 1'b0;
43e4332c
JW
136 cp_rnw = 1'bx;
137 cp_write = 32'hxxxxxxxx;
b114e03f 138 offset = prev_offset;
4d7253f1 139 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
fdecc897 140 next_outcpsrup = cpsrup;
666ceb03 141 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
142 lsrh_rddata_s1 = 16'hxxxx;
143 lsrh_rddata_s2 = 8'hxx;
9a0d0e43
CL
144 next_lsm_state = lsm_state;
145 next_lsr_state = lsr_state;
666ceb03 146 next_lsrh_state = lsrh_state;
9a0d0e43
CL
147 next_swp_oldval = swp_oldval;
148 next_swp_state = swp_state;
149 cur_reg = prev_reg;
9f082c0b 150
ab12fa63
JW
151`define SWP_READING 2'b01
152`define SWP_WRITING 2'b10
153
154`define LSRH_MEMIO 3'b001
155`define LSRH_BASEWB 3'b010
156`define LSRH_WBFLUSH 3'b100
157
158`define LSR_MEMIO 4'b0001
159`define LSR_STRB_WR 4'b0010
160`define LSR_BASEWB 4'b0100
161`define LSR_WBFLUSH 4'b1000
162
163`define LSM_SETUP 4'b0001
164`define LSM_MEMIO 4'b0010
165`define LSM_BASEWB 4'b0100
166`define LSM_WBFLUSH 4'b1000
167
5989b2f5 168 /* XXX shit not given about endianness */
d73619a2 169 casez(insn)
5989b2f5
CL
170 `DECODE_ALU_SWP: if(!inbubble) begin
171 outstall = rw_wait;
172 next_outbubble = rw_wait;
173 busaddr = {op0[31:2], 2'b0};
2bcc55d5 174 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 175 case(swp_state)
ab12fa63 176 `SWP_READING: begin
5989b2f5
CL
177 rd_req = 1'b1;
178 outstall = 1'b1;
179 if(!rw_wait) begin
ab12fa63 180 next_swp_state = `SWP_WRITING;
5989b2f5 181 next_swp_oldval = rd_data;
9a0d0e43 182 end
fb529aac 183 $display("SWP: read stage");
9a0d0e43 184 end
ab12fa63 185 `SWP_WRITING: begin
5989b2f5 186 wr_req = 1'b1;
2bcc55d5 187 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
188 next_write_reg = 1'b1;
189 next_write_num = insn[15:12];
2bcc55d5 190 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5 191 if(!rw_wait)
ab12fa63 192 next_swp_state = `SWP_READING;
fb529aac 193 $display("SWP: write stage");
5989b2f5
CL
194 end
195 default: begin end
196 endcase
9a0d0e43 197 end
fb529aac 198 `DECODE_ALU_MULT: begin end
666ceb03
CL
199 `DECODE_ALU_HDATA_REG,
200 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
201 next_outbubble = rw_wait;
202 outstall = rw_wait;
203 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
204 raddr = insn[24] ? op0 : addr; /* pre/post increment */
205 busaddr = raddr;
206 /* rotate to correct position */
207 case(insn[6:5])
666ceb03
CL
208 2'b01: begin /* unsigned half */
209 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 210 data_size = 3'b010;
666ceb03
CL
211 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
212 end
213 2'b10: begin /* signed byte */
214 wr_data = {4{op2[7:0]}};
2bcc55d5 215 data_size = 3'b001;
666ceb03
CL
216 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
217 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
218 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
219 end
220 2'b11: begin /* signed half */
221 wr_data = {2{op2[15:0]}};
2bcc55d5 222 data_size = 3'b010;
666ceb03
CL
223 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
224 end
ab12fa63
JW
225 default: begin
226 wr_data = 32'hxxxxxxxx;
227 data_size = 3'bxxx;
228 lsrh_rddata = 32'hxxxxxxxx;
229 end
666ceb03
CL
230 endcase
231
232 case(lsrh_state)
ab12fa63 233 `LSRH_MEMIO: begin
666ceb03
CL
234 rd_req = insn[20];
235 wr_req = ~insn[20];
236 next_write_num = insn[15:12];
237 next_write_data = lsrh_rddata;
238 if(insn[20]) begin
239 next_write_reg = 1'b1;
240 end
d64d6ef9 241 if(insn[21] | !insn[24]) begin
666ceb03
CL
242 outstall = 1'b1;
243 if(!rw_wait)
ab12fa63 244 next_lsrh_state = `LSRH_BASEWB;
666ceb03 245 end
fb529aac 246 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
666ceb03 247 end
ab12fa63 248 `LSRH_BASEWB: begin
4d7253f1 249 next_outbubble = 1'b0;
666ceb03
CL
250 next_write_reg = 1'b1;
251 next_write_num = insn[19:16];
252 next_write_data = addr;
ab12fa63 253 next_lsrh_state = `LSRH_WBFLUSH;
4d7253f1 254 end
ab12fa63 255 `LSRH_WBFLUSH: begin
4d7253f1 256 outstall = 0;
ab12fa63 257 next_lsrh_state = `LSRH_MEMIO;
666ceb03
CL
258 end
259 default: begin end
260 endcase
d64d6ef9 261
ab12fa63 262 if ((lsrh_state == `LSRH_MEMIO) && flush) begin /* Reject it. */
d64d6ef9 263 outstall = 1'b0;
ab12fa63 264 next_lsrh_state = `LSRH_MEMIO;
d64d6ef9 265 end
666ceb03 266 end
b3bb2fb8 267 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
268 `DECODE_LDRSTR: if(!inbubble) begin
269 next_outbubble = rw_wait;
270 outstall = rw_wait;
271 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 272 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
273 busaddr = raddr;
274 /* rotate to correct position */
5989b2f5
CL
275 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
276 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
277 /* select byte or word */
278 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
6d18bf27 279 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5 280 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 281 case(lsr_state)
ab12fa63
JW
282
283 `LSR_MEMIO: begin
6d18bf27
JW
284 rd_req = insn[20] /* L */ || insn[22] /* B */;
285 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
fb529aac 286 next_write_reg = insn[20] /* L */;
666ceb03 287 next_write_num = insn[15:12];
fb529aac 288 if(insn[20] /* L */) begin
6d18bf27 289 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
a02ca509 290 end
6d18bf27
JW
291 if (insn[22] /* B */ && !insn[20] /* L */) begin
292 do_rd_data_latch = 1;
293 outstall = 1'b1;
294 if (!rw_wait)
ab12fa63 295 next_lsr_state = `LSR_STRB_WR;
6d18bf27 296 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
5989b2f5
CL
297 outstall = 1'b1;
298 if(!rw_wait)
ab12fa63 299 next_lsr_state = `LSR_BASEWB;
a02ca509 300 end
d73619a2 301 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8 302 end
ab12fa63 303 `LSR_STRB_WR: begin
6d18bf27 304 $display("LDRSTR: Handling STRB");
4d7253f1 305 outstall = 1;
6d18bf27
JW
306 rd_req = 0;
307 wr_req = 1;
308 next_write_reg = 0;
309 case (busaddr[1:0])
310 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
311 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
312 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
313 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
314 endcase
315 if(insn[21] /* W */ | !insn[24] /* P */) begin
316 if(!rw_wait)
ab12fa63 317 next_lsr_state = `LSR_BASEWB;
6d18bf27 318 end else if (!rw_wait)
ab12fa63 319 next_lsr_state = `LSR_WBFLUSH;
6d18bf27 320 end
ab12fa63 321 `LSR_BASEWB: begin
6d18bf27
JW
322 outstall = 1;
323 rd_req = 0;
324 wr_req= 0;
4d7253f1 325 next_outbubble = 0;
5989b2f5
CL
326 next_write_reg = 1'b1;
327 next_write_num = insn[19:16];
328 next_write_data = addr;
ab12fa63 329 next_lsr_state = `LSR_WBFLUSH;
4d7253f1 330 end
ab12fa63 331 `LSR_WBFLUSH: begin
6d18bf27
JW
332 rd_req = 0;
333 wr_req= 0;
4d7253f1 334 outstall = 0;
ab12fa63 335 next_lsr_state = `LSR_MEMIO;
5989b2f5
CL
336 end
337 default: begin end
338 endcase
d64d6ef9 339
ab12fa63 340 if ((lsr_state == `LSR_MEMIO) && flush) begin /* Reject it. */
d64d6ef9 341 outstall = 1'b0;
ab12fa63 342 next_lsr_state = `LSR_MEMIO;
d64d6ef9 343 end
b3bb2fb8 344 end
5989b2f5
CL
345 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
346 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43
CL
347 outstall = rw_wait;
348 next_outbubble = rw_wait;
2bcc55d5 349 data_size = 3'b100;
9a0d0e43 350 case(lsm_state)
ab12fa63 351 `LSM_SETUP: begin
b114e03f
CL
352// next_regs = insn[23] ? op1[15:0] : op1[0:15];
353 /** verilator can suck my dick */
b957d34d
JW
354 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
355 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
356 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 357 offset = 6'b0;
d64d6ef9 358 outstall = 1'b1;
ab12fa63 359 next_lsm_state = `LSM_MEMIO;
e08b748a 360 end
4d7253f1 361 4'b0010: begin
9a0d0e43
CL
362 rd_req = insn[20];
363 wr_req = ~insn[20];
9f082c0b
CL
364 casez(regs)
365 16'b???????????????1: begin
e08b748a 366 cur_reg = 4'h0;
b114e03f 367 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
368 end
369 16'b??????????????10: begin
e08b748a 370 cur_reg = 4'h1;
b114e03f 371 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
372 end
373 16'b?????????????100: begin
e08b748a 374 cur_reg = 4'h2;
b114e03f 375 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
376 end
377 16'b????????????1000: begin
e08b748a 378 cur_reg = 4'h3;
b114e03f 379 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
380 end
381 16'b???????????10000: begin
e08b748a 382 cur_reg = 4'h4;
b114e03f 383 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
384 end
385 16'b??????????100000: begin
e08b748a 386 cur_reg = 4'h5;
b114e03f 387 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
388 end
389 16'b?????????1000000: begin
e08b748a 390 cur_reg = 4'h6;
b114e03f 391 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
392 end
393 16'b????????10000000: begin
e08b748a 394 cur_reg = 4'h7;
b114e03f 395 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
396 end
397 16'b???????100000000: begin
e08b748a 398 cur_reg = 4'h8;
b114e03f 399 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
400 end
401 16'b??????1000000000: begin
e08b748a 402 cur_reg = 4'h9;
b114e03f 403 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
404 end
405 16'b?????10000000000: begin
e08b748a 406 cur_reg = 4'hA;
b114e03f 407 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
408 end
409 16'b????100000000000: begin
e08b748a 410 cur_reg = 4'hB;
b114e03f 411 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
412 end
413 16'b???1000000000000: begin
e08b748a 414 cur_reg = 4'hC;
b114e03f 415 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
416 end
417 16'b??10000000000000: begin
e08b748a 418 cur_reg = 4'hD;
b114e03f 419 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
420 end
421 16'b?100000000000000: begin
e08b748a 422 cur_reg = 4'hE;
b114e03f 423 next_regs = {regs[15], 15'b0};
9f082c0b
CL
424 end
425 16'b1000000000000000: begin
e08b748a 426 cur_reg = 4'hF;
9f082c0b
CL
427 next_regs = 16'b0;
428 end
429 default: begin
e08b748a
CL
430 cur_reg = 4'hx;
431 next_regs = 16'b0;
9f082c0b
CL
432 end
433 endcase
b957d34d 434 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13
CL
435 if(cur_reg == 4'hF && insn[22]) begin
436 next_outcpsr = spsr;
fdecc897 437 next_outcpsrup = 1;
efd1aa13 438 end
b114e03f 439
95704fd3 440 offset = prev_offset + 6'h4;
d73619a2
JW
441 offset_sel = insn[24] ? offset : prev_offset;
442 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
443 if(insn[20]) begin
444 next_write_reg = !rw_wait;
445 next_write_num = cur_reg;
446 next_write_data = rd_data;
447 end
448 if (rw_wait) begin
449 next_regs = regs;
450 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
451 end
452
453 st_read = cur_reg;
b957d34d 454 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 455 busaddr = raddr;
b957d34d 456
d73619a2 457 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43
CL
458
459 outstall = 1'b1;
460
461 if(next_regs == 16'b0) begin
ab12fa63 462 next_lsm_state = `LSM_BASEWB;
9a0d0e43
CL
463 end
464 end
ab12fa63 465 `LSM_BASEWB: begin
4d7253f1
JW
466 outstall = 1;
467 next_outbubble = 0;
b957d34d 468 next_write_reg = insn[21] /* writeback */;
9a0d0e43
CL
469 next_write_num = insn[19:16];
470 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
ab12fa63 471 next_lsm_state = `LSM_WBFLUSH;
d73619a2 472 $display("LDMSTM: Stage 3: Writing back");
b783a475 473 end
ab12fa63 474 `LSM_WBFLUSH: begin
4d7253f1 475 outstall = 0;
ab12fa63 476 next_lsm_state = `LSM_SETUP;
4d7253f1 477 end
d73619a2 478 default: $stop;
9a0d0e43 479 endcase
ab12fa63 480 if ((lsm_state == `LSM_SETUP) && flush) begin /* Reject it. */
d64d6ef9 481 outstall = 1'b0;
ab12fa63 482 next_lsm_state = `LSM_SETUP;
d64d6ef9 483 end
d73619a2 484 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8 485 end
5989b2f5 486 `DECODE_LDCSTC: if(!inbubble) begin
43e4332c
JW
487 $display("WARNING: Unimplemented LDCSTC");
488 end
5989b2f5 489 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
490 cp_req = 1;
491 if (cp_busy) begin
492 outstall = 1;
493 next_outbubble = 1;
494 end
495 if (!cp_ack) begin
496 /* XXX undefined instruction trap */
497 $display("WARNING: Possible CDP undefined instruction");
498 end
499 end
5989b2f5 500 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
501 cp_req = 1;
502 cp_rnw = insn[20] /* L */;
503 if (insn[20] == 0 /* store to coprocessor */)
504 cp_write = op0;
505 else begin
d1d0eb8e
JW
506 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
507 next_write_reg = 1'b1;
508 next_write_num = insn[15:12];
509 next_write_data = cp_read;
fdecc897 510 end else begin
d1d0eb8e 511 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
fdecc897
JW
512 next_outcpsrup = 1;
513 end
43e4332c
JW
514 end
515 if (cp_busy) begin
516 outstall = 1;
517 next_outbubble = 1;
518 end
519 if (!cp_ack) begin
838e283e 520 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 521 end
838e283e 522 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 523 end
b3bb2fb8
CL
524 default: begin end
525 endcase
d73619a2
JW
526
527 if ((flush || delayedflush) && !outstall)
528 next_outbubble = 1'b1;
b3bb2fb8 529 end
b3bb2fb8 530endmodule
This page took 0.123121 seconds and 4 git commands to generate.