Add chip enable correctness for CellularRAM.
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
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3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
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21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
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25 input flush,
26
b3bb2fb8 27 /* bus interface */
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28 output reg [31:0] dc__addr_3a,
29 output reg dc__rd_req_3a,
30 output reg dc__wr_req_3a,
31 input dc__rw_wait_3a,
32 output reg [31:0] dc__wr_data_3a,
33 input [31:0] dc__rd_data_3a,
34 output reg [2:0] dc__data_size_3a,
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35
36 /* regfile interface */
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37 output reg [3:0] rf__read_3_3a,
38 input [31:0] rf__rdata_3_3a,
a02ca509 39
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40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
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45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
a02ca509 48 /* stage inputs */
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49 input bubble_3a,
50 input [31:0] pc_3a,
51 input [31:0] insn_3a,
52 input [31:0] op0_3a,
53 input [31:0] op1_3a,
54 input [31:0] op2_3a,
55 input [31:0] spsr_3a,
56 input [31:0] cpsr_3a,
57 input cpsrup_3a,
58 input write_reg_3a,
59 input [3:0] write_num_3a,
60 input [31:0] write_data_3a,
b3bb2fb8 61
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62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
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66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
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71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
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81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
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87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
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90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
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98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
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100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
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103
104 always @(posedge clk)
105 begin
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106 outpc <= pc_3a;
107 outinsn <= insn_3a;
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108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
b0e4ff00 112 if (!dc__rw_wait_3a)
95704fd3 113 prev_offset <= offset;
b114e03f 114 prev_raddr <= raddr;
ab7ee9fc 115 outcpsr <= next_outcpsr;
b0e4ff00 116 outspsr <= spsr_3a;
fdecc897 117 outcpsrup <= next_outcpsrup;
9a0d0e43 118 swp_state <= next_swp_state;
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119 lsm_state <= next_lsm_state;
120 lsr_state <= next_lsr_state;
121 lsrh_state <= next_lsrh_state;
6d18bf27 122 if (do_rd_data_latch)
b0e4ff00 123 rd_data_latch <= dc__rd_data_3a;
55c6199c 124 swp_oldval <= next_swp_oldval;
666ceb03 125 prevaddr <= addr;
a02ca509 126 end
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127
128 reg delayedflush = 0;
129 always @(posedge clk)
130 if (flush && outstall /* halp! I can't do it now, maybe later? */)
131 delayedflush <= 1;
132 else if (!outstall /* anything has been handled this time around */)
133 delayedflush <= 0;
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134
135 /* Drive the state machines and stall. */
136 always @(*)
137 begin
138 outstall = 1'b0;
139 next_lsm_state = lsm_state;
140 next_lsr_state = lsr_state;
141 next_lsrh_state = lsrh_state;
142 next_swp_state = swp_state;
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143 casez(insn_3a)
144 `DECODE_ALU_SWP: if(!bubble_3a) begin
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145 case(swp_state)
146 `SWP_READING: begin
147 outstall = 1'b1;
b0e4ff00 148 if (!dc__rw_wait_3a)
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149 next_swp_state = `SWP_WRITING;
150 $display("SWP: read stage");
151 end
152 `SWP_WRITING: begin
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153 outstall = dc__rw_wait_3a;
154 if(!dc__rw_wait_3a)
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155 next_swp_state = `SWP_READING;
156 $display("SWP: write stage");
157 end
158 default: begin
159 outstall = 1'bx;
160 next_swp_state = 2'bxx;
161 end
162 endcase
163 end
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164 `DECODE_ALU_MULT: begin
165 outstall = 1'b0; /* XXX work around for Xilinx bug */
166 next_lsrh_state = lsrh_state;
167 end
bb2595ed 168 `DECODE_ALU_HDATA_REG,
b0e4ff00 169 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
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170 case(lsrh_state)
171 `LSRH_MEMIO: begin
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172 outstall = dc__rw_wait_3a;
173 if(insn_3a[21] | !insn_3a[24]) begin
bb2595ed 174 outstall = 1'b1;
b0e4ff00 175 if(!dc__rw_wait_3a)
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176 next_lsrh_state = `LSRH_BASEWB;
177 end
178
179 if (flush) /* special case! */ begin
180 outstall = 1'b0;
181 next_lsrh_state = `LSRH_MEMIO;
182 end
183
b0e4ff00 184 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", dc__rd_req_3a, dc__wr_req_3a);
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185 end
186 `LSRH_BASEWB: begin
187 outstall = 1'b1;
188 next_lsrh_state = `LSRH_WBFLUSH;
189 end
190 `LSRH_WBFLUSH: begin
191 outstall = 1'b0;
192 next_lsrh_state = `LSRH_MEMIO;
193 end
194 default: begin
195 outstall = 1'bx;
196 next_lsrh_state = 3'bxxx;
197 end
198 endcase
199 end
200 `DECODE_LDRSTR_UNDEFINED: begin end
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201 `DECODE_LDRSTR: if(!bubble_3a) begin
202 outstall = dc__rw_wait_3a;
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203 case(lsr_state)
204 `LSR_MEMIO: begin
b0e4ff00 205 outstall = dc__rw_wait_3a;
bb2595ed 206 next_lsr_state = `LSR_MEMIO;
b0e4ff00 207 if (insn_3a[22] /* B */ && !insn_3a[20] /* L */) begin /* i.e., strb */
bb2595ed 208 outstall = 1'b1;
b0e4ff00 209 if (!dc__rw_wait_3a)
bb2595ed 210 next_lsr_state = `LSR_STRB_WR;
b0e4ff00 211 end else if (insn_3a[21] /* W */ || !insn_3a[24] /* P */) begin /* writeback needed */
bb2595ed 212 outstall = 1'b1;
b0e4ff00 213 if (!dc__rw_wait_3a)
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214 next_lsr_state = `LSR_BASEWB;
215 end
216
217 if (flush) begin
218 outstall = 1'b0;
219 next_lsr_state = `LSR_MEMIO;
220 end
b0e4ff00 221 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", dc__rd_req_3a, dc__wr_req_3a, raddr, dc__rw_wait_3a);
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222 end
223 `LSR_STRB_WR: begin
224 outstall = 1;
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225 if(insn_3a[21] /* W */ | !insn_3a[24] /* P */) begin
226 if(!dc__rw_wait_3a)
bb2595ed 227 next_lsr_state = `LSR_BASEWB;
b0e4ff00 228 end else if (!dc__rw_wait_3a)
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229 next_lsr_state = `LSR_WBFLUSH;
230 $display("LDRSTR: Handling STRB");
231 end
232 `LSR_BASEWB: begin
233 outstall = 1;
234 next_lsr_state = `LSR_WBFLUSH;
235 end
236 `LSR_WBFLUSH: begin
237 outstall = 0;
238 next_lsr_state = `LSR_MEMIO;
239 end
240 default: begin
241 outstall = 1'bx;
242 next_lsr_state = 4'bxxxx;
243 end
244 endcase
b0e4ff00 245 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", bubble_3a, insn_3a, lsr_state, next_lsr_state, outstall);
bb2595ed 246 end
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247 `DECODE_LDMSTM: if(!bubble_3a) begin
248 outstall = dc__rw_wait_3a;
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249 case(lsm_state)
250 `LSM_SETUP: begin
251 outstall = 1'b1;
252 next_lsm_state = `LSM_MEMIO;
253 if (flush) begin
254 outstall = 1'b0;
255 next_lsm_state = `LSM_SETUP;
256 end
b0e4ff00 257 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0_3a, op1_3a[15:0]);
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258 end
259 `LSM_MEMIO: begin
260 outstall = 1'b1;
b0e4ff00 261 if(next_regs == 16'b0 && !dc__rw_wait_3a) begin
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262 next_lsm_state = `LSM_BASEWB;
263 end
264
b0e4ff00 265 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, rf__rdata_3_3a, dc__addr_3a);
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266 end
267 `LSM_BASEWB: begin
268 outstall = 1;
269 next_lsm_state = `LSM_WBFLUSH;
270 $display("LDMSTM: Stage 3: Writing back");
271 end
272 `LSM_WBFLUSH: begin
273 outstall = 0;
274 next_lsm_state = `LSM_SETUP;
275 end
276 default: begin
277 outstall = 1'bx;
278 next_lsm_state = 4'bxxxx;
279 end
280 endcase
b0e4ff00 281 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", bubble_3a, insn_3a, lsm_state, next_lsm_state, outstall);
bb2595ed 282 end
b0e4ff00 283 `DECODE_LDCSTC: if(!bubble_3a) begin
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284 $display("WARNING: Unimplemented LDCSTC");
285 end
b0e4ff00 286 `DECODE_CDP: if (!bubble_3a) begin
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287 if (cp_busy) begin
288 outstall = 1;
289 end
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290 if (!cp_ack) begin
291 /* XXX undefined instruction trap */
292 $display("WARNING: Possible CDP undefined instruction");
293 end
bb2595ed 294 end
b0e4ff00 295 `DECODE_MRCMCR: if (!bubble_3a) begin
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296 if (cp_busy) begin
297 outstall = 1;
298 end
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299 if (!cp_ack) begin
300 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
301 end
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302 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
303 end
304 default: begin end
305 endcase
306 end
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307
308 /* Coprocessor input. */
309 always @(*)
310 begin
311 cp_req = 0;
312 cp_rnw = 1'bx;
313 cp_write = 32'hxxxxxxxx;
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314 casez (insn_3a)
315 `DECODE_CDP: if(!bubble_3a) begin
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316 cp_req = 1;
317 end
b0e4ff00 318 `DECODE_MRCMCR: if(!bubble_3a) begin
1ce42ada 319 cp_req = 1;
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320 cp_rnw = insn_3a[20] /* L */;
321 if (insn_3a[20] == 0 /* store to coprocessor */)
322 cp_write = op0_3a;
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323 end
324 endcase
325 end
326
327 /* Register output logic. */
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328 always @(*)
329 begin
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330 next_write_reg = write_reg_3a;
331 next_write_num = write_num_3a;
332 next_write_data = write_data_3a;
333 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
334 next_outcpsrup = cpsrup_3a;
1ce42ada 335
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336 casez(insn_3a)
337 `DECODE_ALU_SWP: if (!bubble_3a) begin
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338 next_write_reg = 1'bx;
339 next_write_num = 4'bxxxx;
340 next_write_data = 32'hxxxxxxxx;
341 case(swp_state)
342 `SWP_READING:
343 next_write_reg = 1'b0;
344 `SWP_WRITING: begin
345 next_write_reg = 1'b1;
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346 next_write_num = insn_3a[15:12];
347 next_write_data = insn_3a[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
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348 end
349 default: begin end
350 endcase
351 end
1092591b 352 `DECODE_ALU_MULT: begin
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353 next_write_reg = write_reg_3a; /* XXX workaround for ISE 10.1 bug */
354 next_write_num = write_num_3a;
355 next_write_data = write_data_3a;
356 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
357 next_outcpsrup = cpsrup_3a;
1092591b 358 end
1ce42ada 359 `DECODE_ALU_HDATA_REG,
b0e4ff00 360 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
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361 next_write_reg = 1'bx;
362 next_write_num = 4'bxxxx;
363 next_write_data = 32'hxxxxxxxx;
364 case(lsrh_state)
365 `LSRH_MEMIO: begin
b0e4ff00 366 next_write_num = insn_3a[15:12];
1ce42ada 367 next_write_data = lsrh_rddata;
b0e4ff00 368 if(insn_3a[20]) begin
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369 next_write_reg = 1'b1;
370 end
371 end
372 `LSRH_BASEWB: begin
373 next_write_reg = 1'b1;
b0e4ff00 374 next_write_num = insn_3a[19:16];
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375 next_write_data = addr;
376 end
377 `LSRH_WBFLUSH:
378 next_write_reg = 1'b0;
379 default: begin end
380 endcase
381 end
382 `DECODE_LDRSTR_UNDEFINED: begin end
b0e4ff00 383 `DECODE_LDRSTR: if(!bubble_3a) begin
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384 next_write_reg = 1'bx;
385 next_write_num = 4'bxxxx;
386 next_write_data = 32'hxxxxxxxx;
387 case(lsr_state)
388 `LSR_MEMIO: begin
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389 next_write_reg = insn_3a[20] /* L */;
390 next_write_num = insn_3a[15:12];
391 if(insn_3a[20] /* L */) begin
392 next_write_data = insn_3a[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
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393 end
394 end
395 `LSR_STRB_WR:
396 next_write_reg = 1'b0;
397 `LSR_BASEWB: begin
398 next_write_reg = 1'b1;
b0e4ff00 399 next_write_num = insn_3a[19:16];
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400 next_write_data = addr;
401 end
402 `LSR_WBFLUSH:
403 next_write_reg = 1'b0;
404 default: begin end
405 endcase
406 end
b0e4ff00 407 `DECODE_LDMSTM: if(!bubble_3a) begin
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408 next_write_reg = 1'bx;
409 next_write_num = 4'bxxxx;
410 next_write_data = 32'hxxxxxxxx;
411 case(lsm_state)
412 `LSM_SETUP:
413 next_write_reg = 1'b0;
414 `LSM_MEMIO: begin
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415 if(insn_3a[20] /* L */) begin
416 next_write_reg = !dc__rw_wait_3a;
1ce42ada 417 next_write_num = cur_reg;
b0e4ff00 418 next_write_data = dc__rd_data_3a;
1ce42ada
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419 end else
420 next_write_reg = 1'b0;
421 end
422 `LSM_BASEWB: begin
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423 next_write_reg = insn_3a[21] /* writeback */;
424 next_write_num = insn_3a[19:16];
425 next_write_data = insn_3a[23] ? op0_3a + {26'b0, prev_offset} : op0_3a - {26'b0, prev_offset};
426 if(cur_reg == 4'hF && insn_3a[22]) begin
427 next_outcpsr = spsr_3a;
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428 next_outcpsrup = 1;
429 end
430 end
431 `LSM_WBFLUSH:
432 next_write_reg = 1'b0;
433 default: begin end
434 endcase
435 end
b0e4ff00 436 `DECODE_MRCMCR: if(!bubble_3a) begin
1ce42ada
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437 next_write_reg = 1'bx;
438 next_write_num = 4'bxxxx;
439 next_write_data = 32'hxxxxxxxx;
440 next_outcpsr = 32'hxxxxxxxx;
441 next_outcpsrup = 1'bx;
b0e4ff00
JW
442 if (insn_3a[20] == 1 /* load from coprocessor */)
443 if (insn_3a[15:12] != 4'hF /* Fuck you ARM */) begin
1ce42ada 444 next_write_reg = 1'b1;
b0e4ff00 445 next_write_num = insn_3a[15:12];
1ce42ada
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446 next_write_data = cp_read;
447 end else begin
b0e4ff00 448 next_outcpsr = {cp_read[31:28], cpsr_3a[27:0]};
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449 next_outcpsrup = 1;
450 end
451 end
452 endcase
453 end
454
50d1792c 455 /* Bus/address control logic. */
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CL
456 always @(*)
457 begin
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JW
458 dc__rd_req_3a = 1'b0;
459 dc__wr_req_3a = 1'b0;
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JW
460 offset = prev_offset;
461 addr = prevaddr;
462 raddr = 32'hxxxxxxxx;
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463 dc__addr_3a = 32'hxxxxxxxx;
464 dc__data_size_3a = 3'bxxx;
1ce42ada 465
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JW
466 casez(insn_3a)
467 `DECODE_ALU_SWP: if(!bubble_3a) begin
468 dc__addr_3a = {op0_3a[31:2], 2'b0};
469 dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
5989b2f5 470 case(swp_state)
33bb0152 471 `SWP_READING:
b0e4ff00 472 dc__rd_req_3a = 1'b1;
50d1792c 473 `SWP_WRITING:
b0e4ff00 474 dc__wr_req_3a = 1'b1;
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CL
475 default: begin end
476 endcase
9a0d0e43 477 end
1092591b 478 `DECODE_ALU_MULT: begin
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JW
479 dc__rd_req_3a = 1'b0; /* XXX workaround for Xilinx bug */
480 dc__wr_req_3a = 1'b0;
1092591b
JW
481 offset = prev_offset;
482 addr = prevaddr;
483 end
666ceb03 484 `DECODE_ALU_HDATA_REG,
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JW
485 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
486 addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
487 raddr = insn_3a[24] ? op0_3a : addr; /* pre/post increment */
488 dc__addr_3a = raddr;
666ceb03 489 /* rotate to correct position */
b0e4ff00 490 case(insn_3a[6:5])
50d1792c 491 2'b01: /* unsigned half */
b0e4ff00 492 dc__data_size_3a = 3'b010;
50d1792c 493 2'b10: /* signed byte */
b0e4ff00 494 dc__data_size_3a = 3'b001;
50d1792c 495 2'b11: /* signed half */
b0e4ff00 496 dc__data_size_3a = 3'b010;
ab12fa63 497 default: begin
b0e4ff00 498 dc__data_size_3a = 3'bxxx;
ab12fa63 499 end
666ceb03 500 endcase
33bb0152 501
666ceb03 502 case(lsrh_state)
ab12fa63 503 `LSRH_MEMIO: begin
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JW
504 dc__rd_req_3a = insn_3a[20];
505 dc__wr_req_3a = ~insn_3a[20];
666ceb03 506 end
33bb0152 507 `LSRH_BASEWB: begin end
1ce42ada 508 `LSRH_WBFLUSH: begin end
666ceb03
CL
509 default: begin end
510 endcase
511 end
b3bb2fb8 512 `DECODE_LDRSTR_UNDEFINED: begin end
b0e4ff00
JW
513 `DECODE_LDRSTR: if(!bubble_3a) begin
514 addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
515 raddr = insn_3a[24] ? addr : op0_3a; /* pre/post increment */
516 dc__addr_3a = raddr;
517 dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
33bb0152 518 case (lsr_state)
ab12fa63 519 `LSR_MEMIO: begin
b0e4ff00
JW
520 dc__rd_req_3a = insn_3a[20] /* L */ || insn_3a[22] /* B */;
521 dc__wr_req_3a = !insn_3a[20] /* L */ && !insn_3a[22]/* B */;
b3bb2fb8 522 end
50d1792c 523 `LSR_STRB_WR:
b0e4ff00 524 dc__wr_req_3a = 1;
33bb0152
JW
525 `LSR_BASEWB: begin end
526 `LSR_WBFLUSH: begin end
527 default: begin end
528 endcase
529 end
b0e4ff00
JW
530 `DECODE_LDMSTM: if (!bubble_3a) begin
531 dc__data_size_3a = 3'b100;
33bb0152 532 case (lsm_state)
463f8162
JW
533 `LSM_SETUP:
534 offset = 6'b0;
33bb0152 535 `LSM_MEMIO: begin
b0e4ff00
JW
536 dc__rd_req_3a = insn_3a[20];
537 dc__wr_req_3a = ~insn_3a[20];
463f8162 538 offset = prev_offset + 6'h4;
b0e4ff00
JW
539 offset_sel = insn_3a[24] ? offset : prev_offset;
540 raddr = insn_3a[23] ? op0_3a + {26'b0, offset_sel} : op0_3a - {26'b0, offset_sel};
541 dc__addr_3a = raddr;
4d7253f1 542 end
33bb0152
JW
543 `LSM_BASEWB: begin end
544 `LSM_WBFLUSH: begin end
545 default: begin end
546 endcase
547 end
548 `DECODE_LDCSTC: begin end
549 `DECODE_CDP: begin end
550 `DECODE_MRCMCR: begin end
551 default: begin end
552 endcase
553 end
554
50d1792c 555 /* Bus data control logic. */
33bb0152
JW
556 always @(*)
557 begin
b0e4ff00 558 dc__wr_data_3a = 32'hxxxxxxxx;
33bb0152 559
b0e4ff00
JW
560 casez(insn_3a)
561 `DECODE_ALU_SWP: if(!bubble_3a)
50d1792c 562 if (swp_state == `SWP_WRITING)
b0e4ff00 563 dc__wr_data_3a = insn_3a[22] ? {4{op1_3a[7:0]}} : op1_3a;
33bb0152
JW
564 `DECODE_ALU_MULT: begin end
565 `DECODE_ALU_HDATA_REG,
b0e4ff00
JW
566 `DECODE_ALU_HDATA_IMM: if(!bubble_3a)
567 case(insn_3a[6:5])
50d1792c 568 2'b01: /* unsigned half */
b0e4ff00 569 dc__wr_data_3a = {2{op2_3a[15:0]}}; /* XXX need to store halfword */
50d1792c 570 2'b10: /* signed byte */
b0e4ff00 571 dc__wr_data_3a = {4{op2_3a[7:0]}};
50d1792c 572 2'b11: /* signed half */
b0e4ff00 573 dc__wr_data_3a = {2{op2_3a[15:0]}};
33bb0152
JW
574 default: begin end
575 endcase
33bb0152 576 `DECODE_LDRSTR_UNDEFINED: begin end
b0e4ff00
JW
577 `DECODE_LDRSTR: if(!bubble_3a) begin
578 dc__wr_data_3a = insn_3a[22] ? {24'h0, {op2_3a[7:0]}} : op2_3a;
50d1792c 579 if (lsr_state == `LSR_STRB_WR)
b0e4ff00
JW
580 case (dc__addr_3a[1:0])
581 2'b00: dc__wr_data_3a = {rd_data_latch[31:8], op2_3a[7:0]};
582 2'b01: dc__wr_data_3a = {rd_data_latch[31:16], op2_3a[7:0], rd_data_latch[7:0]};
583 2'b10: dc__wr_data_3a = {rd_data_latch[31:24], op2_3a[7:0], rd_data_latch[15:0]};
584 2'b11: dc__wr_data_3a = {op2_3a[7:0], rd_data_latch[23:0]};
50d1792c 585 endcase
b3bb2fb8 586 end
b0e4ff00 587 `DECODE_LDMSTM: if (!bubble_3a)
e92804b3 588 if (lsm_state == `LSM_MEMIO)
b0e4ff00 589 dc__wr_data_3a = (cur_reg == 4'hF) ? (pc_3a + 12) : rf__rdata_3_3a;
50d1792c
JW
590 `DECODE_LDCSTC: begin end
591 `DECODE_CDP: begin end
592 `DECODE_MRCMCR: begin end
593 default: begin end
594 endcase
595 end
596
597 /* LDM/STM register control logic. */
e54a317f 598 always @(posedge clk)
b0e4ff00 599 if (!dc__rw_wait_3a || lsm_state != `LSM_MEMIO)
e54a317f
JW
600 begin
601 prev_reg <= cur_reg;
602 regs <= next_regs;
603 end
604
50d1792c
JW
605 always @(*)
606 begin
b0e4ff00 607 rf__read_3_3a = 4'hx;
50d1792c
JW
608 cur_reg = prev_reg;
609 next_regs = regs;
610
b0e4ff00
JW
611 casez(insn_3a)
612 `DECODE_LDMSTM: if(!bubble_3a) begin
9a0d0e43 613 case(lsm_state)
50d1792c 614 `LSM_SETUP:
b0e4ff00
JW
615 next_regs = insn_3a[23] /* U */ ? op1_3a[15:0] : {op1_3a[0], op1_3a[1], op1_3a[2], op1_3a[3], op1_3a[4], op1_3a[5], op1_3a[6], op1_3a[7],
616 op1_3a[8], op1_3a[9], op1_3a[10], op1_3a[11], op1_3a[12], op1_3a[13], op1_3a[14], op1_3a[15]};
bb2595ed 617 `LSM_MEMIO: begin
9f082c0b
CL
618 casez(regs)
619 16'b???????????????1: begin
e08b748a 620 cur_reg = 4'h0;
b114e03f 621 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
622 end
623 16'b??????????????10: begin
e08b748a 624 cur_reg = 4'h1;
b114e03f 625 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
626 end
627 16'b?????????????100: begin
e08b748a 628 cur_reg = 4'h2;
b114e03f 629 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
630 end
631 16'b????????????1000: begin
e08b748a 632 cur_reg = 4'h3;
b114e03f 633 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
634 end
635 16'b???????????10000: begin
e08b748a 636 cur_reg = 4'h4;
b114e03f 637 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
638 end
639 16'b??????????100000: begin
e08b748a 640 cur_reg = 4'h5;
b114e03f 641 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
642 end
643 16'b?????????1000000: begin
e08b748a 644 cur_reg = 4'h6;
b114e03f 645 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
646 end
647 16'b????????10000000: begin
e08b748a 648 cur_reg = 4'h7;
b114e03f 649 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
650 end
651 16'b???????100000000: begin
e08b748a 652 cur_reg = 4'h8;
b114e03f 653 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
654 end
655 16'b??????1000000000: begin
e08b748a 656 cur_reg = 4'h9;
b114e03f 657 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
658 end
659 16'b?????10000000000: begin
e08b748a 660 cur_reg = 4'hA;
b114e03f 661 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
662 end
663 16'b????100000000000: begin
e08b748a 664 cur_reg = 4'hB;
b114e03f 665 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
666 end
667 16'b???1000000000000: begin
e08b748a 668 cur_reg = 4'hC;
b114e03f 669 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
670 end
671 16'b??10000000000000: begin
e08b748a 672 cur_reg = 4'hD;
b114e03f 673 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
674 end
675 16'b?100000000000000: begin
e08b748a 676 cur_reg = 4'hE;
b114e03f 677 next_regs = {regs[15], 15'b0};
9f082c0b
CL
678 end
679 16'b1000000000000000: begin
e08b748a 680 cur_reg = 4'hF;
9f082c0b
CL
681 next_regs = 16'b0;
682 end
683 default: begin
e08b748a
CL
684 cur_reg = 4'hx;
685 next_regs = 16'b0;
9f082c0b
CL
686 end
687 endcase
b0e4ff00 688 cur_reg = insn_3a[23] ? cur_reg : 4'hF - cur_reg;
50d1792c 689
b0e4ff00 690 rf__read_3_3a = cur_reg;
9a0d0e43 691 end
50d1792c
JW
692 `LSM_BASEWB: begin end
693 `LSM_WBFLUSH: begin end
694 default: begin end
695 endcase
696 end
697 endcase
698 end
699
700 always @(*)
701 begin
50d1792c
JW
702 do_rd_data_latch = 0;
703
b0e4ff00 704 next_outbubble = bubble_3a;
50d1792c
JW
705
706 lsrh_rddata = 32'hxxxxxxxx;
707 lsrh_rddata_s1 = 16'hxxxx;
708 lsrh_rddata_s2 = 8'hxx;
709 next_swp_oldval = swp_oldval;
55c6199c
JW
710
711 align_s1 = 32'hxxxxxxxx;
712 align_s2 = 32'hxxxxxxxx;
713 align_rddata = 32'hxxxxxxxx;
50d1792c
JW
714
715 /* XXX shit not given about endianness */
b0e4ff00
JW
716 casez(insn_3a)
717 `DECODE_ALU_SWP: if(!bubble_3a) begin
718 next_outbubble = dc__rw_wait_3a;
50d1792c
JW
719 case(swp_state)
720 `SWP_READING:
b0e4ff00
JW
721 if(!dc__rw_wait_3a)
722 next_swp_oldval = dc__rd_data_3a;
50d1792c
JW
723 `SWP_WRITING: begin end
724 default: begin end
725 endcase
726 end
1092591b 727 `DECODE_ALU_MULT: begin
b0e4ff00 728 next_outbubble = bubble_3a; /* XXX workaround for Xilinx bug */
1092591b 729 end
50d1792c 730 `DECODE_ALU_HDATA_REG,
b0e4ff00
JW
731 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
732 next_outbubble = dc__rw_wait_3a;
50d1792c
JW
733
734 /* rotate to correct position */
b0e4ff00 735 case(insn_3a[6:5])
50d1792c 736 2'b01: begin /* unsigned half */
b0e4ff00 737 lsrh_rddata = {16'b0, raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0]};
50d1792c
JW
738 end
739 2'b10: begin /* signed byte */
b0e4ff00 740 lsrh_rddata_s1 = raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0];
50d1792c
JW
741 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
742 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
743 end
744 2'b11: begin /* signed half */
b0e4ff00 745 lsrh_rddata = raddr[1] ? {{16{dc__rd_data_3a[31]}}, dc__rd_data_3a[31:16]} : {{16{dc__rd_data_3a[15]}}, dc__rd_data_3a[15:0]};
50d1792c
JW
746 end
747 default: begin
748 lsrh_rddata = 32'hxxxxxxxx;
749 end
750 endcase
751
752 case(lsrh_state)
753 `LSRH_MEMIO: begin end
754 `LSRH_BASEWB:
755 next_outbubble = 1'b0;
756 `LSRH_WBFLUSH: begin end
757 default: begin end
758 endcase
759 end
760 `DECODE_LDRSTR_UNDEFINED: begin end
b0e4ff00
JW
761 `DECODE_LDRSTR: if(!bubble_3a) begin
762 next_outbubble = dc__rw_wait_3a;
50d1792c 763 /* rotate to correct position */
b0e4ff00 764 align_s1 = raddr[1] ? {dc__rd_data_3a[15:0], dc__rd_data_3a[31:16]} : dc__rd_data_3a;
50d1792c
JW
765 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
766 /* select byte or word */
b0e4ff00 767 align_rddata = insn_3a[22] ? {24'b0, align_s2[7:0]} : align_s2;
50d1792c
JW
768 case(lsr_state)
769 `LSR_MEMIO:
b0e4ff00 770 if (insn_3a[22] /* B */ && !insn_3a[20] /* L */)
50d1792c
JW
771 do_rd_data_latch = 1;
772 `LSR_STRB_WR: begin end
773 `LSR_BASEWB:
774 next_outbubble = 0;
775 `LSR_WBFLUSH: begin end
776 default: begin end
777 endcase
778 end
779 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
b0e4ff00
JW
780 `DECODE_LDMSTM: if(!bubble_3a) begin
781 next_outbubble = dc__rw_wait_3a;
50d1792c
JW
782 case(lsm_state)
783 `LSM_SETUP: begin end
784 `LSM_MEMIO: begin end
1ce42ada 785 `LSM_BASEWB:
4d7253f1 786 next_outbubble = 0;
bb2595ed 787 `LSM_WBFLUSH: begin end
d73619a2 788 default: $stop;
9a0d0e43 789 endcase
43e4332c 790 end
bb2595ed 791 `DECODE_LDCSTC: begin end
b0e4ff00 792 `DECODE_CDP: if(!bubble_3a) begin
43e4332c 793 if (cp_busy) begin
43e4332c
JW
794 next_outbubble = 1;
795 end
43e4332c 796 end
b0e4ff00 797 `DECODE_MRCMCR: if(!bubble_3a) begin
43e4332c 798 if (cp_busy) begin
43e4332c
JW
799 next_outbubble = 1;
800 end
43e4332c 801 end
b3bb2fb8
CL
802 default: begin end
803 endcase
d73619a2
JW
804
805 if ((flush || delayedflush) && !outstall)
806 next_outbubble = 1'b1;
b3bb2fb8 807 end
b3bb2fb8 808endmodule
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