memory: ldm/stm bullSHIT
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
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6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
14
15 /* regfile interface */
16 output reg [3:0] st_read,
17 input [31:0] st_data,
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18
19 /* stage inputs */
20 input inbubble,
21 input [31:0] pc,
22 input [31:0] insn,
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23 input [31:0] op0,
24 input [31:0] op1,
6d0f9d82 25 input [31:0] op2,
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26 input [31:0] spsr,
27 input [31:0] cpsr,
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28 input write_reg,
29 input [3:0] write_num,
30 input [31:0] write_data,
b3bb2fb8 31
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32 /* outputs */
33 output reg outstall,
34 output reg outbubble,
b3bb2fb8 35 output reg [31:0] outpc,
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36 output reg [31:0] outinsn,
37 output reg out_write_reg = 1'b0,
38 output reg [3:0] out_write_num = 4'bxxxx,
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39 output reg [31:0] out_write_data = 32'hxxxxxxxx,
40 output reg [31:0] out_spsr = 32'hxxxxxxxx,
41 output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509 42 );
b3bb2fb8 43
efd1aa13 44 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
e08b748a 45 reg [3:0] next_regsel, cur_reg, prev_reg;
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46 reg next_writeback, next_notdone, next_inc_next;
47 reg [31:0] align_s1, align_s2, align_rddata;
e08b748a 48
c65110a8 49 wire next_outbubble;
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50 wire next_write_reg;
51 wire [3:0] next_write_num;
52 wire [31:0] next_write_data;
74d3729c 53
b783a475 54 reg [15:0] regs, next_regs;
e08b748a 55 reg started = 1'b0, next_started;
b114e03f 56 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 57
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58 reg notdone = 1'b0;
59 reg inc_next = 1'b0;
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60
61 always @(posedge clk)
62 begin
63 outpc <= pc;
64 outinsn <= insn;
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65 outbubble <= next_outbubble;
66 out_write_reg <= next_write_reg;
67 out_write_num <= next_write_num;
68 out_write_data <= next_write_data;
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69 notdone <= next_notdone;
70 inc_next <= next_inc_next;
e68b2378 71 regs <= next_regs;
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72 prev_reg <= cur_reg;
73 started <= next_started;
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74 prev_offset <= offset;
75 prev_raddr <= raddr;
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76 out_cpsr <= next_outcpsr;
77 out_spsr <= spsr;
a02ca509 78 end
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79
80 always @(*)
81 begin
82 addr = 32'hxxxxxxxx;
83 raddr = 32'hxxxxxxxx;
84 rd_req = 1'b0;
85 wr_req = 1'b0;
86 wr_data = 32'hxxxxxxxx;
87 busaddr = 32'hxxxxxxxx;
88 outstall = 1'b0;
74d3729c 89 next_notdone = 1'b0;
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90 next_write_reg = write_reg;
91 next_write_num = write_num;
92 next_write_data = write_data;
74d3729c 93 next_inc_next = 1'b0;
c65110a8 94 next_outbubble = inbubble;
a02ca509 95 outstall = 1'b0;
9f082c0b 96 next_regs = 16'b0;
e08b748a 97 next_started = started;
b114e03f 98 offset = prev_offset;
efd1aa13 99 next_outcpsr = started ? out_cpsr : cpsr;
9f082c0b 100
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101 casez(insn)
102 `DECODE_LDRSTR_UNDEFINED: begin end
103 `DECODE_LDRSTR: begin
a02ca509 104 if (!inbubble) begin
c65110a8 105 next_outbubble = rw_wait;
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106 outstall = rw_wait | notdone;
107
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108 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
109 raddr = insn[24] ? op0 : addr; /* pre/post increment */
110 busaddr = {raddr[31:2], 2'b0};
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111 rd_req = insn[20];
112 wr_req = ~insn[20];
113
114 /* rotate to correct position */
115 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
116 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
117 /* select byte or word */
118 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
119
120 if(!insn[20]) begin
6d0f9d82 121 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
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122 end
123 else if(!inc_next) begin
124 next_write_reg = 1'b1;
125 next_write_num = insn[15:12];
126 next_write_data = align_rddata;
127 next_inc_next = 1'b1;
128 end
129 else if(insn[21]) begin
130 next_write_reg = 1'b1;
131 next_write_num = insn[19:16];
132 next_write_data = addr;
133 end
134 next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8 135 end
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136 end
137 `DECODE_LDMSTM: begin
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138 rd_req = insn[20];
139 wr_req = ~insn[20];
e08b748a 140 if(!started) begin
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141// next_regs = insn[23] ? op1[15:0] : op1[0:15];
142 /** verilator can suck my dick */
143 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
144 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
145 offset = 6'b0;
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146 next_started = 1'b1;
147 end
148 else if(inc_next) begin
149 if(insn[21]) begin
150 next_write_reg = 1'b1;
151 next_write_num = insn[19:16];
b114e03f 152 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
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153 end
154 next_started = 1'b0;
b783a475 155 end
e08b748a 156 else if(rw_wait) begin
9f082c0b 157 next_regs = regs;
e08b748a 158 cur_reg = prev_reg;
b114e03f 159 raddr = prev_raddr;
e08b748a 160 end
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161 else begin
162 casez(regs)
163 16'b???????????????1: begin
e08b748a 164 cur_reg = 4'h0;
b114e03f 165 next_regs = {regs[15:1], 1'b0};
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166 end
167 16'b??????????????10: begin
e08b748a 168 cur_reg = 4'h1;
b114e03f 169 next_regs = {regs[15:2], 2'b0};
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170 end
171 16'b?????????????100: begin
e08b748a 172 cur_reg = 4'h2;
b114e03f 173 next_regs = {regs[15:3], 3'b0};
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174 end
175 16'b????????????1000: begin
e08b748a 176 cur_reg = 4'h3;
b114e03f 177 next_regs = {regs[15:4], 4'b0};
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178 end
179 16'b???????????10000: begin
e08b748a 180 cur_reg = 4'h4;
b114e03f 181 next_regs = {regs[15:5], 5'b0};
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182 end
183 16'b??????????100000: begin
e08b748a 184 cur_reg = 4'h5;
b114e03f 185 next_regs = {regs[15:6], 6'b0};
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186 end
187 16'b?????????1000000: begin
e08b748a 188 cur_reg = 4'h6;
b114e03f 189 next_regs = {regs[15:7], 7'b0};
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190 end
191 16'b????????10000000: begin
e08b748a 192 cur_reg = 4'h7;
b114e03f 193 next_regs = {regs[15:8], 8'b0};
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194 end
195 16'b???????100000000: begin
e08b748a 196 cur_reg = 4'h8;
b114e03f 197 next_regs = {regs[15:9], 9'b0};
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198 end
199 16'b??????1000000000: begin
e08b748a 200 cur_reg = 4'h9;
b114e03f 201 next_regs = {regs[15:10], 10'b0};
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202 end
203 16'b?????10000000000: begin
e08b748a 204 cur_reg = 4'hA;
b114e03f 205 next_regs = {regs[15:11], 11'b0};
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206 end
207 16'b????100000000000: begin
e08b748a 208 cur_reg = 4'hB;
b114e03f 209 next_regs = {regs[15:12], 12'b0};
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210 end
211 16'b???1000000000000: begin
e08b748a 212 cur_reg = 4'hC;
b114e03f 213 next_regs = {regs[15:13], 13'b0};
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214 end
215 16'b??10000000000000: begin
e08b748a 216 cur_reg = 4'hD;
b114e03f 217 next_regs = {regs[15:14], 14'b0};
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218 end
219 16'b?100000000000000: begin
e08b748a 220 cur_reg = 4'hE;
b114e03f 221 next_regs = {regs[15], 15'b0};
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222 end
223 16'b1000000000000000: begin
e08b748a 224 cur_reg = 4'hF;
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225 next_regs = 16'b0;
226 end
227 default: begin
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228 cur_reg = 4'hx;
229 next_regs = 16'b0;
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230 end
231 endcase
b114e03f 232 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
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233 if(cur_reg == 4'hF && insn[22]) begin
234 next_outcpsr = spsr;
235 end
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236 offset = prev_offset + 6'h4;
237 offset_sel = insn[24] ? offset : prev_offset;
238 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
239
240 if(insn[20]) begin
241 next_write_reg = 1'b1;
242 next_write_num = cur_reg;
243 next_write_data = rd_data;
244 end
245
246 st_read = cur_reg;
247 wr_data = st_data;
248
9f082c0b 249 next_inc_next = next_regs == 16'b0;
efd1aa13 250 next_notdone = ~next_inc_next | rw_wait;
b114e03f 251 busaddr = {raddr[31:2], 2'b0};
b783a475 252 end
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253 end
254 default: begin end
255 endcase
256 end
b3bb2fb8 257endmodule
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