Memory: Fix up latch logic for LDM/STM.
[firearm.git] / Memory.v
CommitLineData
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1`include "ARM_Constants.v"
2
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3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
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21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
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25 input flush,
26
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27 /* bus interface */
28 output reg [31:0] busaddr,
29 output reg rd_req,
30 output reg wr_req,
31 input rw_wait,
32 output reg [31:0] wr_data,
33 input [31:0] rd_data,
9fc6c23c 34 output reg [2:0] data_size,
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35
36 /* regfile interface */
37 output reg [3:0] st_read,
38 input [31:0] st_data,
a02ca509 39
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40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
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45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
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48 /* stage inputs */
49 input inbubble,
50 input [31:0] pc,
51 input [31:0] insn,
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52 input [31:0] op0,
53 input [31:0] op1,
6d0f9d82 54 input [31:0] op2,
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55 input [31:0] spsr,
56 input [31:0] cpsr,
fdecc897 57 input cpsrup,
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58 input write_reg,
59 input [3:0] write_num,
60 input [31:0] write_data,
b3bb2fb8 61
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62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
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66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
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71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
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81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
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87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
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90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
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98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
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100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
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103
104 always @(posedge clk)
105 begin
106 outpc <= pc;
107 outinsn <= insn;
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108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
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112 if (!rw_wait)
113 prev_offset <= offset;
b114e03f 114 prev_raddr <= raddr;
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115 outcpsr <= next_outcpsr;
116 outspsr <= spsr;
fdecc897 117 outcpsrup <= next_outcpsrup;
9a0d0e43 118 swp_state <= next_swp_state;
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119 lsm_state <= next_lsm_state;
120 lsr_state <= next_lsr_state;
121 lsrh_state <= next_lsrh_state;
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122 if (do_rd_data_latch)
123 rd_data_latch <= rd_data;
666ceb03 124 prevaddr <= addr;
a02ca509 125 end
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126
127 reg delayedflush = 0;
128 always @(posedge clk)
129 if (flush && outstall /* halp! I can't do it now, maybe later? */)
130 delayedflush <= 1;
131 else if (!outstall /* anything has been handled this time around */)
132 delayedflush <= 0;
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133
134 /* Drive the state machines and stall. */
135 always @(*)
136 begin
137 outstall = 1'b0;
138 next_lsm_state = lsm_state;
139 next_lsr_state = lsr_state;
140 next_lsrh_state = lsrh_state;
141 next_swp_state = swp_state;
142 casez(insn)
143 `DECODE_ALU_SWP: if(!inbubble) begin
144 case(swp_state)
145 `SWP_READING: begin
146 outstall = 1'b1;
147 if (!rw_wait)
148 next_swp_state = `SWP_WRITING;
149 $display("SWP: read stage");
150 end
151 `SWP_WRITING: begin
152 outstall = rw_wait;
153 if(!rw_wait)
154 next_swp_state = `SWP_READING;
155 $display("SWP: write stage");
156 end
157 default: begin
158 outstall = 1'bx;
159 next_swp_state = 2'bxx;
160 end
161 endcase
162 end
163 `DECODE_ALU_MULT: begin end
164 `DECODE_ALU_HDATA_REG,
165 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
166 case(lsrh_state)
167 `LSRH_MEMIO: begin
168 outstall = rw_wait;
169 if(insn[21] | !insn[24]) begin
170 outstall = 1'b1;
171 if(!rw_wait)
172 next_lsrh_state = `LSRH_BASEWB;
173 end
174
175 if (flush) /* special case! */ begin
176 outstall = 1'b0;
177 next_lsrh_state = `LSRH_MEMIO;
178 end
179
180 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
181 end
182 `LSRH_BASEWB: begin
183 outstall = 1'b1;
184 next_lsrh_state = `LSRH_WBFLUSH;
185 end
186 `LSRH_WBFLUSH: begin
187 outstall = 1'b0;
188 next_lsrh_state = `LSRH_MEMIO;
189 end
190 default: begin
191 outstall = 1'bx;
192 next_lsrh_state = 3'bxxx;
193 end
194 endcase
195 end
196 `DECODE_LDRSTR_UNDEFINED: begin end
197 `DECODE_LDRSTR: if(!inbubble) begin
198 outstall = rw_wait;
199 case(lsr_state)
200 `LSR_MEMIO: begin
201 outstall = rw_wait;
202 next_lsr_state = `LSR_MEMIO;
203 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
204 outstall = 1'b1;
205 if (!rw_wait)
206 next_lsr_state = `LSR_STRB_WR;
207 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
208 outstall = 1'b1;
209 if (!rw_wait)
210 next_lsr_state = `LSR_BASEWB;
211 end
212
213 if (flush) begin
214 outstall = 1'b0;
215 next_lsr_state = `LSR_MEMIO;
216 end
217 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
218 end
219 `LSR_STRB_WR: begin
220 outstall = 1;
221 if(insn[21] /* W */ | !insn[24] /* P */) begin
222 if(!rw_wait)
223 next_lsr_state = `LSR_BASEWB;
224 end else if (!rw_wait)
225 next_lsr_state = `LSR_WBFLUSH;
226 $display("LDRSTR: Handling STRB");
227 end
228 `LSR_BASEWB: begin
229 outstall = 1;
230 next_lsr_state = `LSR_WBFLUSH;
231 end
232 `LSR_WBFLUSH: begin
233 outstall = 0;
234 next_lsr_state = `LSR_MEMIO;
235 end
236 default: begin
237 outstall = 1'bx;
238 next_lsr_state = 4'bxxxx;
239 end
240 endcase
241 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
242 end
243 `DECODE_LDMSTM: if(!inbubble) begin
244 outstall = rw_wait;
245 case(lsm_state)
246 `LSM_SETUP: begin
247 outstall = 1'b1;
248 next_lsm_state = `LSM_MEMIO;
249 if (flush) begin
250 outstall = 1'b0;
251 next_lsm_state = `LSM_SETUP;
252 end
253 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
254 end
255 `LSM_MEMIO: begin
256 outstall = 1'b1;
257 if(next_regs == 16'b0) begin
258 next_lsm_state = `LSM_BASEWB;
259 end
260
261 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
262 end
263 `LSM_BASEWB: begin
264 outstall = 1;
265 next_lsm_state = `LSM_WBFLUSH;
266 $display("LDMSTM: Stage 3: Writing back");
267 end
268 `LSM_WBFLUSH: begin
269 outstall = 0;
270 next_lsm_state = `LSM_SETUP;
271 end
272 default: begin
273 outstall = 1'bx;
274 next_lsm_state = 4'bxxxx;
275 end
276 endcase
277 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
278 end
279 `DECODE_LDCSTC: if(!inbubble) begin
280 $display("WARNING: Unimplemented LDCSTC");
281 end
282 `DECODE_CDP: if (!inbubble) begin
283 if (cp_busy) begin
284 outstall = 1;
285 end
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286 if (!cp_ack) begin
287 /* XXX undefined instruction trap */
288 $display("WARNING: Possible CDP undefined instruction");
289 end
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290 end
291 `DECODE_MRCMCR: if (!inbubble) begin
292 if (cp_busy) begin
293 outstall = 1;
294 end
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295 if (!cp_ack) begin
296 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
297 end
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298 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
299 end
300 default: begin end
301 endcase
302 end
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303
304 /* Coprocessor input. */
305 always @(*)
306 begin
307 cp_req = 0;
308 cp_rnw = 1'bx;
309 cp_write = 32'hxxxxxxxx;
310 casez (insn)
311 `DECODE_CDP: if(!inbubble) begin
312 cp_req = 1;
313 end
314 `DECODE_MRCMCR: if(!inbubble) begin
315 cp_req = 1;
316 cp_rnw = insn[20] /* L */;
317 if (insn[20] == 0 /* store to coprocessor */)
318 cp_write = op0;
319 end
320 endcase
321 end
322
323 /* Register output logic. */
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324 always @(*)
325 begin
326 next_write_reg = write_reg;
327 next_write_num = write_num;
328 next_write_data = write_data;
329 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
330 next_outcpsrup = cpsrup;
331
332 casez(insn)
333 `DECODE_ALU_SWP: if (!inbubble) begin
334 next_write_reg = 1'bx;
335 next_write_num = 4'bxxxx;
336 next_write_data = 32'hxxxxxxxx;
337 case(swp_state)
338 `SWP_READING:
339 next_write_reg = 1'b0;
340 `SWP_WRITING: begin
341 next_write_reg = 1'b1;
342 next_write_num = insn[15:12];
343 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
344 end
345 default: begin end
346 endcase
347 end
348 `DECODE_ALU_MULT: begin end
349 `DECODE_ALU_HDATA_REG,
350 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
351 next_write_reg = 1'bx;
352 next_write_num = 4'bxxxx;
353 next_write_data = 32'hxxxxxxxx;
354 case(lsrh_state)
355 `LSRH_MEMIO: begin
356 next_write_num = insn[15:12];
357 next_write_data = lsrh_rddata;
358 if(insn[20]) begin
359 next_write_reg = 1'b1;
360 end
361 end
362 `LSRH_BASEWB: begin
363 next_write_reg = 1'b1;
364 next_write_num = insn[19:16];
365 next_write_data = addr;
366 end
367 `LSRH_WBFLUSH:
368 next_write_reg = 1'b0;
369 default: begin end
370 endcase
371 end
372 `DECODE_LDRSTR_UNDEFINED: begin end
373 `DECODE_LDRSTR: if(!inbubble) begin
374 next_write_reg = 1'bx;
375 next_write_num = 4'bxxxx;
376 next_write_data = 32'hxxxxxxxx;
377 case(lsr_state)
378 `LSR_MEMIO: begin
379 next_write_reg = insn[20] /* L */;
380 next_write_num = insn[15:12];
381 if(insn[20] /* L */) begin
382 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
383 end
384 end
385 `LSR_STRB_WR:
386 next_write_reg = 1'b0;
387 `LSR_BASEWB: begin
388 next_write_reg = 1'b1;
389 next_write_num = insn[19:16];
390 next_write_data = addr;
391 end
392 `LSR_WBFLUSH:
393 next_write_reg = 1'b0;
394 default: begin end
395 endcase
396 end
397 `DECODE_LDMSTM: if(!inbubble) begin
398 next_write_reg = 1'bx;
399 next_write_num = 4'bxxxx;
400 next_write_data = 32'hxxxxxxxx;
401 case(lsm_state)
402 `LSM_SETUP:
403 next_write_reg = 1'b0;
404 `LSM_MEMIO: begin
405 if(insn[20]) begin
406 next_write_reg = !rw_wait;
407 next_write_num = cur_reg;
408 next_write_data = rd_data;
409 end else
410 next_write_reg = 1'b0;
411 end
412 `LSM_BASEWB: begin
413 next_write_reg = insn[21] /* writeback */;
414 next_write_num = insn[19:16];
415 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
416 if(cur_reg == 4'hF && insn[22]) begin
417 next_outcpsr = spsr;
418 next_outcpsrup = 1;
419 end
420 end
421 `LSM_WBFLUSH:
422 next_write_reg = 1'b0;
423 default: begin end
424 endcase
425 end
426 `DECODE_MRCMCR: if(!inbubble) begin
427 next_write_reg = 1'bx;
428 next_write_num = 4'bxxxx;
429 next_write_data = 32'hxxxxxxxx;
430 next_outcpsr = 32'hxxxxxxxx;
431 next_outcpsrup = 1'bx;
432 if (insn[20] == 1 /* load from coprocessor */)
433 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
434 next_write_reg = 1'b1;
435 next_write_num = insn[15:12];
436 next_write_data = cp_read;
437 end else begin
438 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
439 next_outcpsrup = 1;
440 end
441 end
442 endcase
443 end
444
50d1792c 445 /* Bus/address control logic. */
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CL
446 always @(*)
447 begin
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448 rd_req = 1'b0;
449 wr_req = 1'b0;
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450 offset = prev_offset;
451 addr = prevaddr;
452 raddr = 32'hxxxxxxxx;
b3bb2fb8 453 busaddr = 32'hxxxxxxxx;
2bcc55d5 454 data_size = 3'bxxx;
1ce42ada 455
d73619a2 456 casez(insn)
5989b2f5 457 `DECODE_ALU_SWP: if(!inbubble) begin
5989b2f5 458 busaddr = {op0[31:2], 2'b0};
2bcc55d5 459 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 460 case(swp_state)
33bb0152 461 `SWP_READING:
5989b2f5 462 rd_req = 1'b1;
50d1792c 463 `SWP_WRITING:
5989b2f5 464 wr_req = 1'b1;
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CL
465 default: begin end
466 endcase
9a0d0e43 467 end
fb529aac 468 `DECODE_ALU_MULT: begin end
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469 `DECODE_ALU_HDATA_REG,
470 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
463f8162
JW
471 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
472 raddr = insn[24] ? op0 : addr; /* pre/post increment */
666ceb03
CL
473 busaddr = raddr;
474 /* rotate to correct position */
475 case(insn[6:5])
50d1792c 476 2'b01: /* unsigned half */
2bcc55d5 477 data_size = 3'b010;
50d1792c 478 2'b10: /* signed byte */
2bcc55d5 479 data_size = 3'b001;
50d1792c 480 2'b11: /* signed half */
2bcc55d5 481 data_size = 3'b010;
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482 default: begin
483 wr_data = 32'hxxxxxxxx;
484 data_size = 3'bxxx;
ab12fa63 485 end
666ceb03 486 endcase
33bb0152 487
666ceb03 488 case(lsrh_state)
ab12fa63 489 `LSRH_MEMIO: begin
666ceb03
CL
490 rd_req = insn[20];
491 wr_req = ~insn[20];
666ceb03 492 end
33bb0152 493 `LSRH_BASEWB: begin end
1ce42ada 494 `LSRH_WBFLUSH: begin end
666ceb03
CL
495 default: begin end
496 endcase
497 end
b3bb2fb8 498 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 499 `DECODE_LDRSTR: if(!inbubble) begin
463f8162
JW
500 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
501 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 502 busaddr = raddr;
6d18bf27 503 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5 504 data_size = insn[22] ? 3'b001 : 3'b100;
33bb0152 505 case (lsr_state)
ab12fa63 506 `LSR_MEMIO: begin
6d18bf27
JW
507 rd_req = insn[20] /* L */ || insn[22] /* B */;
508 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
b3bb2fb8 509 end
50d1792c 510 `LSR_STRB_WR:
6d18bf27 511 wr_req = 1;
33bb0152
JW
512 `LSR_BASEWB: begin end
513 `LSR_WBFLUSH: begin end
514 default: begin end
515 endcase
516 end
517 `DECODE_LDMSTM: if (!inbubble) begin
518 data_size = 3'b100;
519 case (lsm_state)
463f8162
JW
520 `LSM_SETUP:
521 offset = 6'b0;
33bb0152
JW
522 `LSM_MEMIO: begin
523 rd_req = insn[20];
524 wr_req = ~insn[20];
463f8162
JW
525 offset = prev_offset + 6'h4;
526 offset_sel = insn[24] ? offset : prev_offset;
527 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
33bb0152 528 busaddr = raddr;
4d7253f1 529 end
33bb0152
JW
530 `LSM_BASEWB: begin end
531 `LSM_WBFLUSH: begin end
532 default: begin end
533 endcase
534 end
535 `DECODE_LDCSTC: begin end
536 `DECODE_CDP: begin end
537 `DECODE_MRCMCR: begin end
538 default: begin end
539 endcase
540 end
541
50d1792c 542 /* Bus data control logic. */
33bb0152
JW
543 always @(*)
544 begin
50d1792c 545 wr_data = 32'hxxxxxxxx;
33bb0152 546
33bb0152 547 casez(insn)
50d1792c
JW
548 `DECODE_ALU_SWP: if(!inbubble)
549 if (swp_state == `SWP_WRITING)
550 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
33bb0152
JW
551 `DECODE_ALU_MULT: begin end
552 `DECODE_ALU_HDATA_REG,
50d1792c 553 `DECODE_ALU_HDATA_IMM: if(!inbubble)
33bb0152 554 case(insn[6:5])
50d1792c
JW
555 2'b01: /* unsigned half */
556 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
557 2'b10: /* signed byte */
558 wr_data = {4{op2[7:0]}};
559 2'b11: /* signed half */
560 wr_data = {2{op2[15:0]}};
33bb0152
JW
561 default: begin end
562 endcase
33bb0152
JW
563 `DECODE_LDRSTR_UNDEFINED: begin end
564 `DECODE_LDRSTR: if(!inbubble) begin
50d1792c
JW
565 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
566 if (lsr_state == `LSR_STRB_WR)
567 case (busaddr[1:0])
568 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
569 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
570 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
571 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
572 endcase
b3bb2fb8 573 end
50d1792c
JW
574 `DECODE_LDMSTM: if (!inbubble)
575 if (lsr_state == `LSM_MEMIO)
576 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
577 `DECODE_LDCSTC: begin end
578 `DECODE_CDP: begin end
579 `DECODE_MRCMCR: begin end
580 default: begin end
581 endcase
582 end
583
584 /* LDM/STM register control logic. */
e54a317f 585 always @(posedge clk)
8e30fdaf 586 if (!rw_wait || lsm_state != `LSM_MEMIO)
e54a317f
JW
587 begin
588 prev_reg <= cur_reg;
589 regs <= next_regs;
590 end
591
50d1792c
JW
592 always @(*)
593 begin
594 offset = prev_offset;
595 cur_reg = prev_reg;
596 next_regs = regs;
597
598 casez(insn)
5989b2f5 599 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 600 case(lsm_state)
50d1792c 601 `LSM_SETUP:
b957d34d
JW
602 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
603 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
bb2595ed 604 `LSM_MEMIO: begin
9f082c0b
CL
605 casez(regs)
606 16'b???????????????1: begin
e08b748a 607 cur_reg = 4'h0;
b114e03f 608 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
609 end
610 16'b??????????????10: begin
e08b748a 611 cur_reg = 4'h1;
b114e03f 612 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
613 end
614 16'b?????????????100: begin
e08b748a 615 cur_reg = 4'h2;
b114e03f 616 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
617 end
618 16'b????????????1000: begin
e08b748a 619 cur_reg = 4'h3;
b114e03f 620 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
621 end
622 16'b???????????10000: begin
e08b748a 623 cur_reg = 4'h4;
b114e03f 624 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
625 end
626 16'b??????????100000: begin
e08b748a 627 cur_reg = 4'h5;
b114e03f 628 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
629 end
630 16'b?????????1000000: begin
e08b748a 631 cur_reg = 4'h6;
b114e03f 632 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
633 end
634 16'b????????10000000: begin
e08b748a 635 cur_reg = 4'h7;
b114e03f 636 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
637 end
638 16'b???????100000000: begin
e08b748a 639 cur_reg = 4'h8;
b114e03f 640 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
641 end
642 16'b??????1000000000: begin
e08b748a 643 cur_reg = 4'h9;
b114e03f 644 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
645 end
646 16'b?????10000000000: begin
e08b748a 647 cur_reg = 4'hA;
b114e03f 648 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
649 end
650 16'b????100000000000: begin
e08b748a 651 cur_reg = 4'hB;
b114e03f 652 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
653 end
654 16'b???1000000000000: begin
e08b748a 655 cur_reg = 4'hC;
b114e03f 656 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
657 end
658 16'b??10000000000000: begin
e08b748a 659 cur_reg = 4'hD;
b114e03f 660 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
661 end
662 16'b?100000000000000: begin
e08b748a 663 cur_reg = 4'hE;
b114e03f 664 next_regs = {regs[15], 15'b0};
9f082c0b
CL
665 end
666 16'b1000000000000000: begin
e08b748a 667 cur_reg = 4'hF;
9f082c0b
CL
668 next_regs = 16'b0;
669 end
670 default: begin
e08b748a
CL
671 cur_reg = 4'hx;
672 next_regs = 16'b0;
9f082c0b
CL
673 end
674 endcase
b957d34d 675 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
50d1792c 676
b114e03f 677 st_read = cur_reg;
9a0d0e43 678 end
50d1792c
JW
679 `LSM_BASEWB: begin end
680 `LSM_WBFLUSH: begin end
681 default: begin end
682 endcase
683 end
684 endcase
685 end
686
687 always @(*)
688 begin
689 st_read = 4'hx;
690 do_rd_data_latch = 0;
691
692 next_outbubble = inbubble;
693
694 lsrh_rddata = 32'hxxxxxxxx;
695 lsrh_rddata_s1 = 16'hxxxx;
696 lsrh_rddata_s2 = 8'hxx;
697 next_swp_oldval = swp_oldval;
698
699 /* XXX shit not given about endianness */
700 casez(insn)
701 `DECODE_ALU_SWP: if(!inbubble) begin
702 next_outbubble = rw_wait;
703 case(swp_state)
704 `SWP_READING:
705 if(!rw_wait)
706 next_swp_oldval = rd_data;
707 `SWP_WRITING: begin end
708 default: begin end
709 endcase
710 end
711 `DECODE_ALU_MULT: begin end
712 `DECODE_ALU_HDATA_REG,
713 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
714 next_outbubble = rw_wait;
715
716 /* rotate to correct position */
717 case(insn[6:5])
718 2'b01: begin /* unsigned half */
719 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
720 end
721 2'b10: begin /* signed byte */
722 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
723 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
724 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
725 end
726 2'b11: begin /* signed half */
727 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
728 end
729 default: begin
730 lsrh_rddata = 32'hxxxxxxxx;
731 end
732 endcase
733
734 case(lsrh_state)
735 `LSRH_MEMIO: begin end
736 `LSRH_BASEWB:
737 next_outbubble = 1'b0;
738 `LSRH_WBFLUSH: begin end
739 default: begin end
740 endcase
741 end
742 `DECODE_LDRSTR_UNDEFINED: begin end
743 `DECODE_LDRSTR: if(!inbubble) begin
744 next_outbubble = rw_wait;
745 /* rotate to correct position */
746 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
747 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
748 /* select byte or word */
749 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
750 case(lsr_state)
751 `LSR_MEMIO:
752 if (insn[22] /* B */ && !insn[20] /* L */)
753 do_rd_data_latch = 1;
754 `LSR_STRB_WR: begin end
755 `LSR_BASEWB:
756 next_outbubble = 0;
757 `LSR_WBFLUSH: begin end
758 default: begin end
759 endcase
760 end
761 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
762 `DECODE_LDMSTM: if(!inbubble) begin
763 next_outbubble = rw_wait;
764 case(lsm_state)
765 `LSM_SETUP: begin end
766 `LSM_MEMIO: begin end
1ce42ada 767 `LSM_BASEWB:
4d7253f1 768 next_outbubble = 0;
bb2595ed 769 `LSM_WBFLUSH: begin end
d73619a2 770 default: $stop;
9a0d0e43 771 endcase
43e4332c 772 end
bb2595ed 773 `DECODE_LDCSTC: begin end
5989b2f5 774 `DECODE_CDP: if(!inbubble) begin
43e4332c 775 if (cp_busy) begin
43e4332c
JW
776 next_outbubble = 1;
777 end
43e4332c 778 end
5989b2f5 779 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c 780 if (cp_busy) begin
43e4332c
JW
781 next_outbubble = 1;
782 end
43e4332c 783 end
b3bb2fb8
CL
784 default: begin end
785 endcase
d73619a2
JW
786
787 if ((flush || delayedflush) && !outstall)
788 next_outbubble = 1'b1;
b3bb2fb8 789 end
b3bb2fb8 790endmodule
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