Merge branch 'master' of nyus.joshuawise.com:/git/firearm
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8
CL
6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
14
15 /* regfile interface */
16 output reg [3:0] st_read,
17 input [31:0] st_data,
a02ca509
JW
18
19 /* stage inputs */
20 input inbubble,
21 input [31:0] pc,
22 input [31:0] insn,
e68b2378
JW
23 input [31:0] op0,
24 input [31:0] op1,
6d0f9d82 25 input [31:0] op2,
a02ca509
JW
26 input write_reg,
27 input [3:0] write_num,
28 input [31:0] write_data,
b3bb2fb8 29
a02ca509
JW
30 /* outputs */
31 output reg outstall,
32 output reg outbubble,
b3bb2fb8 33 output reg [31:0] outpc,
a02ca509
JW
34 output reg [31:0] outinsn,
35 output reg out_write_reg = 1'b0,
36 output reg [3:0] out_write_num = 4'bxxxx,
37 output reg [31:0] out_write_data = 32'hxxxxxxxx
38 );
b3bb2fb8 39
5bcb3b7e 40 reg [31:0] addr, raddr, next_regdata;
74d3729c
CL
41 reg [3:0] next_regsel;
42 reg next_writeback, next_notdone, next_inc_next;
43 reg [31:0] align_s1, align_s2, align_rddata;
a02ca509
JW
44
45 wire next_write_reg;
46 wire [3:0] next_write_num;
47 wire [31:0] next_write_data;
74d3729c 48
b783a475 49 reg [15:0] regs, next_regs;
74d3729c 50
b3bb2fb8
CL
51 reg notdone = 1'b0;
52 reg inc_next = 1'b0;
a02ca509
JW
53
54 always @(posedge clk)
55 begin
56 outpc <= pc;
57 outinsn <= insn;
58 outbubble <= rw_wait;
59 out_write_reg <= next_writeback;
60 out_write_num <= next_regsel;
61 out_write_data <= next_regdata;
62 notdone <= next_notdone;
63 inc_next <= next_inc_next;
e68b2378 64 regs <= next_regs;
a02ca509 65 end
b3bb2fb8
CL
66
67 always @(*)
68 begin
69 addr = 32'hxxxxxxxx;
70 raddr = 32'hxxxxxxxx;
71 rd_req = 1'b0;
72 wr_req = 1'b0;
73 wr_data = 32'hxxxxxxxx;
74 busaddr = 32'hxxxxxxxx;
75 outstall = 1'b0;
74d3729c 76 next_notdone = 1'b0;
a02ca509
JW
77 next_write_reg = write_reg;
78 next_write_num = write_num;
79 next_write_data = write_data;
74d3729c 80 next_inc_next = 1'b0;
a02ca509 81 outstall = 1'b0;
9f082c0b
CL
82 next_regs = 16'b0;
83
b3bb2fb8
CL
84 casez(insn)
85 `DECODE_LDRSTR_UNDEFINED: begin end
86 `DECODE_LDRSTR: begin
a02ca509
JW
87 if (!inbubble) begin
88 outstall = rw_wait | notdone;
89
e68b2378
JW
90 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
91 raddr = insn[24] ? op0 : addr; /* pre/post increment */
92 busaddr = {raddr[31:2], 2'b0};
a02ca509
JW
93 rd_req = insn[20];
94 wr_req = ~insn[20];
95
96 /* rotate to correct position */
97 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
98 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
99 /* select byte or word */
100 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
101
102 if(!insn[20]) begin
6d0f9d82 103 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
a02ca509
JW
104 end
105 else if(!inc_next) begin
106 next_write_reg = 1'b1;
107 next_write_num = insn[15:12];
108 next_write_data = align_rddata;
109 next_inc_next = 1'b1;
110 end
111 else if(insn[21]) begin
112 next_write_reg = 1'b1;
113 next_write_num = insn[19:16];
114 next_write_data = addr;
115 end
116 next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8 117 end
b3bb2fb8
CL
118 end
119 `DECODE_LDMSTM: begin
b783a475
CL
120 busaddr = {op0[31:2], 2'b0};
121 rd_req = insn[20];
122 wr_req = ~insn[20];
9f082c0b 123 if(inc_next) begin
b783a475 124 end
9f082c0b
CL
125 else if(rw_wait)
126 next_regs = regs;
127 else begin
128 casez(regs)
129 16'b???????????????1: begin
130 next_regs = regs & 16'b1111111111111110;
131 end
132 16'b??????????????10: begin
133 next_regs = regs & 16'b1111111111111100;
134 end
135 16'b?????????????100: begin
136 next_regs = regs & 16'b1111111111111000;
137 end
138 16'b????????????1000: begin
139 next_regs = regs & 16'b1111111111110000;
140 end
141 16'b???????????10000: begin
142 next_regs = regs & 16'b1111111111100000;
143 end
144 16'b??????????100000: begin
145 next_regs = regs & 16'b1111111111000000;
146 end
147 16'b?????????1000000: begin
148 next_regs = regs & 16'b1111111110000000;
149 end
150 16'b????????10000000: begin
151 next_regs = regs & 16'b1111111100000000;
152 end
153 16'b???????100000000: begin
154 next_regs = regs & 16'b1111111000000000;
155 end
156 16'b??????1000000000: begin
157 next_regs = regs & 16'b1111110000000000;
158 end
159 16'b?????10000000000: begin
160 next_regs = regs & 16'b1111100000000000;
161 end
162 16'b????100000000000: begin
163 next_regs = regs & 16'b1111000000000000;
164 end
165 16'b???1000000000000: begin
166 next_regs = regs & 16'b1110000000000000;
167 end
168 16'b??10000000000000: begin
169 next_regs = regs & 16'b1100000000000000;
170 end
171 16'b?100000000000000: begin
172 next_regs = regs & 16'b1000000000000000;
173 end
174 16'b1000000000000000: begin
175 next_regs = 16'b0;
176 end
177 default: begin
178 end
179 endcase
180 next_inc_next = next_regs == 16'b0;
181 next_notdone = ~next_inc_next;
b783a475 182 end
b3bb2fb8
CL
183 end
184 default: begin end
185 endcase
186 end
b3bb2fb8 187endmodule
This page took 0.034369 seconds and 4 git commands to generate.