[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	output reg [31:0] out_cpsr = 32'hxxxxxxxx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback, next_notdone, next_inc_next;
	reg [31:0] align_s1, align_s2, align_rddata;

	wire next_outbubble;	
	wire next_write_reg;
	wire [3:0] next_write_num;
	wire [31:0] next_write_data;

	reg [15:0] regs, next_regs;
	reg started = 1'b0, next_started;
	reg [5:0] offset, prev_offset, offset_sel;

	reg notdone = 1'b0;
	reg inc_next = 1'b0;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		notdone <= next_notdone;
		inc_next <= next_inc_next;
		regs <= next_regs;
		prev_reg <= cur_reg;
		started <= next_started;
		prev_offset <= offset;
		prev_raddr <= raddr;
		out_cpsr <= next_outcpsr;
		out_spsr <= spsr;
	end

	always @(*)
	begin
		addr = 32'hxxxxxxxx;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		outstall = 1'b0;
		next_notdone = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_inc_next = 1'b0;
		next_outbubble = inbubble;
		outstall = 1'b0;
		next_regs = 16'b0;
		next_started = started;
		cp_req = 1'b0;
		offset = prev_offset;
		next_outcpsr = started ? out_cpsr : cpsr;

		casez(insn)
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: begin
			if (!inbubble) begin
				next_outbubble = rw_wait;
				outstall = rw_wait | notdone;
			
				addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
				raddr = insn[24] ? op0 : addr; /* pre/post increment */
				busaddr = {raddr[31:2], 2'b0};
				rd_req = insn[20];
				wr_req = ~insn[20];
				
				/* rotate to correct position */
				align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
				align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
				/* select byte or word */
				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
				
				if(!insn[20]) begin
					wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
				end
				else if(!inc_next) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = align_rddata;
					next_inc_next = 1'b1;
				end
				else if(insn[21]) begin
					next_write_reg = 1'b1;
					next_write_num = insn[19:16];
					next_write_data = addr;
				end
				next_notdone = rw_wait & insn[20] & insn[21];
			end
		end
		`DECODE_LDMSTM: begin
			rd_req = insn[20];
			wr_req = ~insn[20];
			if(!started) begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                    op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				next_started = 1'b1;
			end
			else if(inc_next) begin
				if(insn[21]) begin
					next_write_reg = 1'b1;
					next_write_num = insn[19:16];
					next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				end
				next_started = 1'b0;
			end
			else if(rw_wait) begin
				next_regs = regs;
				cur_reg = prev_reg;
				raddr = prev_raddr;
			end
			else begin
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
				end
				offset = prev_offset + 6'h4;
				offset_sel = insn[24] ? offset : prev_offset;
				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};

				if(insn[20]) begin
					next_write_reg = 1'b1;
					next_write_num = cur_reg;
					next_write_data = rd_data;
				end

				st_read = cur_reg;
				wr_data = st_data;

				next_inc_next = next_regs == 16'b0;
				next_notdone = ~next_inc_next | rw_wait;
				busaddr = {raddr[31:2], 2'b0};
			end
		end
		default: begin end
		endcase
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8 CL	6
	7	/* bus interface */
	8	output reg [31:0] busaddr,
	9	output reg rd_req,
	10	output reg wr_req,
	11	input rw_wait,
	12	output reg [31:0] wr_data,
	13	input [31:0] rd_data,
	14
	15	/* regfile interface */
	16	output reg [3:0] st_read,
	17	input [31:0] st_data,
a02ca509	18
979f2bd7 JW	19	/* Coprocessor interface */
	20	output reg cp_req,
	21	input cp_ack,
	22	input cp_busy,
	23
a02ca509 JW	24	/* stage inputs */
	25	input inbubble,
	26	input [31:0] pc,
	27	input [31:0] insn,
e68b2378 JW	28	input [31:0] op0,
e68b2378 JW	29	input [31:0] op1,
6d0f9d82	30	input [31:0] op2,
efd1aa13 CL	31	input [31:0] spsr,
efd1aa13 CL	32	input [31:0] cpsr,
a02ca509 JW	33	input write_reg,
	34	input [3:0] write_num,
	35	input [31:0] write_data,
b3bb2fb8	36
a02ca509 JW	37	/* outputs */
	38	output reg outstall,
	39	output reg outbubble,
b3bb2fb8	40	output reg [31:0] outpc,
a02ca509 JW	41	output reg [31:0] outinsn,
	42	output reg out_write_reg = 1'b0,
	43	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 CL	44	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	45	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	46	output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509	47	);
b3bb2fb8	48
efd1aa13	49	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
e08b748a	50	reg [3:0] next_regsel, cur_reg, prev_reg;
74d3729c CL	51	reg next_writeback, next_notdone, next_inc_next;
74d3729c CL	52	reg [31:0] align_s1, align_s2, align_rddata;
e08b748a	53
c65110a8	54	wire next_outbubble;
a02ca509 JW	55	wire next_write_reg;
	56	wire [3:0] next_write_num;
	57	wire [31:0] next_write_data;
74d3729c	58
b783a475	59	reg [15:0] regs, next_regs;
e08b748a	60	reg started = 1'b0, next_started;
b114e03f	61	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	62
b3bb2fb8 CL	63	reg notdone = 1'b0;
b3bb2fb8 CL	64	reg inc_next = 1'b0;
a02ca509 JW	65
	66	always @(posedge clk)
	67	begin
	68	outpc <= pc;
	69	outinsn <= insn;
c65110a8 JW	70	outbubble <= next_outbubble;
	71	out_write_reg <= next_write_reg;
	72	out_write_num <= next_write_num;
	73	out_write_data <= next_write_data;
a02ca509 JW	74	notdone <= next_notdone;
a02ca509 JW	75	inc_next <= next_inc_next;
e68b2378	76	regs <= next_regs;
e08b748a CL	77	prev_reg <= cur_reg;
e08b748a CL	78	started <= next_started;
b114e03f CL	79	prev_offset <= offset;
b114e03f CL	80	prev_raddr <= raddr;
efd1aa13 CL	81	out_cpsr <= next_outcpsr;
efd1aa13 CL	82	out_spsr <= spsr;
a02ca509	83	end
b3bb2fb8 CL	84
	85	always @(*)
	86	begin
	87	addr = 32'hxxxxxxxx;
	88	raddr = 32'hxxxxxxxx;
	89	rd_req = 1'b0;
	90	wr_req = 1'b0;
	91	wr_data = 32'hxxxxxxxx;
	92	busaddr = 32'hxxxxxxxx;
	93	outstall = 1'b0;
74d3729c	94	next_notdone = 1'b0;
a02ca509 JW	95	next_write_reg = write_reg;
	96	next_write_num = write_num;
	97	next_write_data = write_data;
74d3729c	98	next_inc_next = 1'b0;
c65110a8	99	next_outbubble = inbubble;
a02ca509	100	outstall = 1'b0;
9f082c0b	101	next_regs = 16'b0;
e08b748a	102	next_started = started;
979f2bd7	103	cp_req = 1'b0;
b114e03f	104	offset = prev_offset;
efd1aa13	105	next_outcpsr = started ? out_cpsr : cpsr;
9f082c0b	106
b3bb2fb8 CL	107	casez(insn)
	108	`DECODE_LDRSTR_UNDEFINED: begin end
	109	`DECODE_LDRSTR: begin
a02ca509	110	if (!inbubble) begin
c65110a8	111	next_outbubble = rw_wait;
a02ca509 JW	112	outstall = rw_wait \| notdone;
a02ca509 JW	113
e68b2378 JW	114	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	115	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	116	busaddr = {raddr[31:2], 2'b0};
a02ca509 JW	117	rd_req = insn[20];
	118	wr_req = ~insn[20];
	119
	120	/* rotate to correct position */
	121	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	122	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	123	/* select byte or word */
	124	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
	125
	126	if(!insn[20]) begin
6d0f9d82	127	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
a02ca509 JW	128	end
	129	else if(!inc_next) begin
	130	next_write_reg = 1'b1;
	131	next_write_num = insn[15:12];
	132	next_write_data = align_rddata;
	133	next_inc_next = 1'b1;
	134	end
	135	else if(insn[21]) begin
	136	next_write_reg = 1'b1;
	137	next_write_num = insn[19:16];
	138	next_write_data = addr;
	139	end
	140	next_notdone = rw_wait & insn[20] & insn[21];
b3bb2fb8	141	end
b3bb2fb8 CL	142	end
b3bb2fb8 CL	143	`DECODE_LDMSTM: begin
b783a475 CL	144	rd_req = insn[20];
b783a475 CL	145	wr_req = ~insn[20];
e08b748a	146	if(!started) begin
b114e03f CL	147	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
	148	/** verilator can suck my dick */
	149	next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	150	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
	151	offset = 6'b0;
e08b748a CL	152	next_started = 1'b1;
	153	end
	154	else if(inc_next) begin
	155	if(insn[21]) begin
	156	next_write_reg = 1'b1;
	157	next_write_num = insn[19:16];
b114e03f	158	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
e08b748a CL	159	end
e08b748a CL	160	next_started = 1'b0;
b783a475	161	end
e08b748a	162	else if(rw_wait) begin
9f082c0b	163	next_regs = regs;
e08b748a	164	cur_reg = prev_reg;
b114e03f	165	raddr = prev_raddr;
e08b748a	166	end
9f082c0b CL	167	else begin
	168	casez(regs)
	169	16'b???????????????1: begin
e08b748a	170	cur_reg = 4'h0;
b114e03f	171	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	172	end
9f082c0b CL	173	16'b??????????????10: begin
e08b748a	174	cur_reg = 4'h1;
b114e03f	175	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	176	end
9f082c0b CL	177	16'b?????????????100: begin
e08b748a	178	cur_reg = 4'h2;
b114e03f	179	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	180	end
9f082c0b CL	181	16'b????????????1000: begin
e08b748a	182	cur_reg = 4'h3;
b114e03f	183	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	184	end
9f082c0b CL	185	16'b???????????10000: begin
e08b748a	186	cur_reg = 4'h4;
b114e03f	187	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	188	end
9f082c0b CL	189	16'b??????????100000: begin
e08b748a	190	cur_reg = 4'h5;
b114e03f	191	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	192	end
9f082c0b CL	193	16'b?????????1000000: begin
e08b748a	194	cur_reg = 4'h6;
b114e03f	195	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	196	end
9f082c0b CL	197	16'b????????10000000: begin
e08b748a	198	cur_reg = 4'h7;
b114e03f	199	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	200	end
9f082c0b CL	201	16'b???????100000000: begin
e08b748a	202	cur_reg = 4'h8;
b114e03f	203	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	204	end
9f082c0b CL	205	16'b??????1000000000: begin
e08b748a	206	cur_reg = 4'h9;
b114e03f	207	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	208	end
9f082c0b CL	209	16'b?????10000000000: begin
e08b748a	210	cur_reg = 4'hA;
b114e03f	211	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	212	end
9f082c0b CL	213	16'b????100000000000: begin
e08b748a	214	cur_reg = 4'hB;
b114e03f	215	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	216	end
9f082c0b CL	217	16'b???1000000000000: begin
e08b748a	218	cur_reg = 4'hC;
b114e03f	219	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	220	end
9f082c0b CL	221	16'b??10000000000000: begin
e08b748a	222	cur_reg = 4'hD;
b114e03f	223	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	224	end
9f082c0b CL	225	16'b?100000000000000: begin
e08b748a	226	cur_reg = 4'hE;
b114e03f	227	next_regs = {regs[15], 15'b0};
9f082c0b CL	228	end
9f082c0b CL	229	16'b1000000000000000: begin
e08b748a	230	cur_reg = 4'hF;
9f082c0b CL	231	next_regs = 16'b0;
	232	end
	233	default: begin
e08b748a CL	234	cur_reg = 4'hx;
e08b748a CL	235	next_regs = 16'b0;
9f082c0b CL	236	end
9f082c0b CL	237	endcase
b114e03f	238	cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
efd1aa13 CL	239	if(cur_reg == 4'hF && insn[22]) begin
	240	next_outcpsr = spsr;
	241	end
b114e03f CL	242	offset = prev_offset + 6'h4;
	243	offset_sel = insn[24] ? offset : prev_offset;
	244	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	245
	246	if(insn[20]) begin
	247	next_write_reg = 1'b1;
	248	next_write_num = cur_reg;
	249	next_write_data = rd_data;
	250	end
	251
	252	st_read = cur_reg;
	253	wr_data = st_data;
	254
9f082c0b	255	next_inc_next = next_regs == 16'b0;
efd1aa13	256	next_notdone = ~next_inc_next \| rw_wait;
b114e03f	257	busaddr = {raddr[31:2], 2'b0};
b783a475	258	end
b3bb2fb8 CL	259	end
	260	default: begin end
	261	endcase
	262	end
b3bb2fb8	263	endmodule