[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	output reg [31:0] out_cpsr = 32'hxxxxxxxx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;
	reg [31:0] align_s1, align_s2, align_rddata;

	wire next_outbubble;	
	wire next_write_reg;
	wire [3:0] next_write_num;
	wire [31:0] next_write_data;

	reg [1:0] lsr_state = 2'b01, next_lsr_state;

	reg [15:0] regs, next_regs;
	reg [2:0] lsm_state = 3'b001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		prev_offset <= offset;
		prev_raddr <= raddr;
		out_cpsr <= next_outcpsr;
		out_spsr <= spsr;
		swp_state <= next_swp_state;
	end

	always @(*)
	begin
		addr = 32'hxxxxxxxx;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		outstall = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		outstall = 1'b0;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		casez(insn)
		`DECODE_ALU_SWP: begin
			if(!inbubble) begin
				outstall = rw_wait;
				next_outbubble = rw_wait;
				busaddr = {op0[31:2], 2'b0};
				case(swp_state)
				2'b01: begin
					rd_req = 1'b1;
					outstall = 1'b1;
					if(!rw_wait) begin
						next_swp_state = 2'b10;
						next_swp_oldval = rd_data;
					end
				end
				2'b10: begin
					wr_req = 1'b1;
					wr_data = op1;
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = swp_oldval;
					if(!rw_wait)
						next_swp_state = 2'b01;
				end
				default: begin end
				endcase
			end
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: begin
			if (!inbubble) begin
				next_outbubble = rw_wait;
				outstall = rw_wait;
				addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
				raddr = insn[24] ? op0 : addr; /* pre/post increment */
				busaddr = {raddr[31:2], 2'b0};

				/* rotate to correct position */
				align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
				align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
				/* select byte or word */
				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
				if(!insn[20]) begin
					wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
				end
				case(lsr_state)
				2'b01: begin
					rd_req = insn[20];
					wr_req = ~insn[20];

					if(insn[20]) begin
						next_write_reg = 1'b1;
						next_write_num = insn[15:12];
						next_write_data = align_rddata;
					end

					if(insn[21]) begin
						outstall = 1'b1;
						if(!rw_wait)
							next_lsr_state = 2'b10;
					end
				end
				2'b10: begin
					next_write_reg = 1'b1;
					next_write_num = insn[19:16];
					next_write_data = addr;
					next_lsr_state = 2'b10;
				end
				default: begin end
				endcase
			end
		end
		`DECODE_LDMSTM: begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			case(lsm_state)
			3'b001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                    op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 3'b010;
			end
			3'b010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
				end

				if(rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;
					raddr = prev_raddr;
				end
				else begin
					offset = prev_offset + 6'h4;
					offset_sel = insn[24] ? offset : prev_offset;
					raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
					if(insn[20]) begin
						next_write_reg = 1'b1;
						next_write_num = cur_reg;
						next_write_data = rd_data;
					end
				end

				st_read = cur_reg;
				wr_data = st_data;
				busaddr = {raddr[31:2], 2'b0};

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 3'b100;
				end
			end
			3'b100: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 3'b001;
			end
			default: begin end
			endcase
		end
		`DECODE_LDCSTC: begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = cp_read;
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction");
			end
		end
		default: begin end
		endcase
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8 CL	6
	7	/* bus interface */
	8	output reg [31:0] busaddr,
	9	output reg rd_req,
	10	output reg wr_req,
	11	input rw_wait,
	12	output reg [31:0] wr_data,
	13	input [31:0] rd_data,
	14
	15	/* regfile interface */
	16	output reg [3:0] st_read,
	17	input [31:0] st_data,
a02ca509	18
979f2bd7 JW	19	/* Coprocessor interface */
	20	output reg cp_req,
	21	input cp_ack,
	22	input cp_busy,
43e4332c JW	23	output cp_rnw, /* 1 = read from CP, 0 = write to CP */
	24	input [31:0] cp_read,
	25	output reg [31:0] cp_write,
979f2bd7	26
a02ca509 JW	27	/* stage inputs */
	28	input inbubble,
	29	input [31:0] pc,
	30	input [31:0] insn,
e68b2378 JW	31	input [31:0] op0,
e68b2378 JW	32	input [31:0] op1,
6d0f9d82	33	input [31:0] op2,
efd1aa13 CL	34	input [31:0] spsr,
efd1aa13 CL	35	input [31:0] cpsr,
a02ca509 JW	36	input write_reg,
	37	input [3:0] write_num,
	38	input [31:0] write_data,
b3bb2fb8	39
a02ca509 JW	40	/* outputs */
	41	output reg outstall,
	42	output reg outbubble,
b3bb2fb8	43	output reg [31:0] outpc,
a02ca509 JW	44	output reg [31:0] outinsn,
	45	output reg out_write_reg = 1'b0,
	46	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 CL	47	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	48	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	49	output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509	50	);
b3bb2fb8	51
efd1aa13	52	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
e08b748a	53	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	54	reg next_writeback;
74d3729c	55	reg [31:0] align_s1, align_s2, align_rddata;
e08b748a	56
c65110a8	57	wire next_outbubble;
a02ca509 JW	58	wire next_write_reg;
	59	wire [3:0] next_write_num;
	60	wire [31:0] next_write_data;
74d3729c	61
9a0d0e43 CL	62	reg [1:0] lsr_state = 2'b01, next_lsr_state;
9a0d0e43 CL	63
b783a475	64	reg [15:0] regs, next_regs;
9a0d0e43	65	reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f	66	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	67
9a0d0e43 CL	68	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	69	reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509 JW	70
	71	always @(posedge clk)
	72	begin
	73	outpc <= pc;
	74	outinsn <= insn;
c65110a8 JW	75	outbubble <= next_outbubble;
	76	out_write_reg <= next_write_reg;
	77	out_write_num <= next_write_num;
	78	out_write_data <= next_write_data;
e68b2378	79	regs <= next_regs;
e08b748a	80	prev_reg <= cur_reg;
b114e03f CL	81	prev_offset <= offset;
b114e03f CL	82	prev_raddr <= raddr;
efd1aa13 CL	83	out_cpsr <= next_outcpsr;
efd1aa13 CL	84	out_spsr <= spsr;
9a0d0e43	85	swp_state <= next_swp_state;
a02ca509	86	end
b3bb2fb8 CL	87
	88	always @(*)
	89	begin
	90	addr = 32'hxxxxxxxx;
	91	raddr = 32'hxxxxxxxx;
	92	rd_req = 1'b0;
	93	wr_req = 1'b0;
	94	wr_data = 32'hxxxxxxxx;
	95	busaddr = 32'hxxxxxxxx;
	96	outstall = 1'b0;
a02ca509 JW	97	next_write_reg = write_reg;
	98	next_write_num = write_num;
	99	next_write_data = write_data;
c65110a8	100	next_outbubble = inbubble;
a02ca509	101	outstall = 1'b0;
9a0d0e43	102	next_regs = regs;
979f2bd7	103	cp_req = 1'b0;
43e4332c JW	104	cp_rnw = 1'bx;
43e4332c JW	105	cp_write = 32'hxxxxxxxx;
b114e03f	106	offset = prev_offset;
9a0d0e43 CL	107	next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
	108	next_lsm_state = lsm_state;
	109	next_lsr_state = lsr_state;
	110	next_swp_oldval = swp_oldval;
	111	next_swp_state = swp_state;
	112	cur_reg = prev_reg;
9f082c0b	113
b3bb2fb8	114	casez(insn)
9a0d0e43 CL	115	`DECODE_ALU_SWP: begin
	116	if(!inbubble) begin
	117	outstall = rw_wait;
	118	next_outbubble = rw_wait;
	119	busaddr = {op0[31:2], 2'b0};
	120	case(swp_state)
	121	2'b01: begin
	122	rd_req = 1'b1;
	123	outstall = 1'b1;
	124	if(!rw_wait) begin
	125	next_swp_state = 2'b10;
	126	next_swp_oldval = rd_data;
	127	end
	128	end
	129	2'b10: begin
	130	wr_req = 1'b1;
	131	wr_data = op1;
	132	next_write_reg = 1'b1;
	133	next_write_num = insn[15:12];
	134	next_write_data = swp_oldval;
	135	if(!rw_wait)
	136	next_swp_state = 2'b01;
	137	end
	138	default: begin end
	139	endcase
	140	end
	141	end
b3bb2fb8 CL	142	`DECODE_LDRSTR_UNDEFINED: begin end
b3bb2fb8 CL	143	`DECODE_LDRSTR: begin
a02ca509	144	if (!inbubble) begin
c65110a8	145	next_outbubble = rw_wait;
9a0d0e43	146	outstall = rw_wait;
e68b2378 JW	147	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	148	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	149	busaddr = {raddr[31:2], 2'b0};
9a0d0e43	150
a02ca509 JW	151	/* rotate to correct position */
	152	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	153	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	154	/* select byte or word */
	155	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
a02ca509	156	if(!insn[20]) begin
6d0f9d82	157	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
a02ca509	158	end
9a0d0e43 CL	159	case(lsr_state)
	160	2'b01: begin
	161	rd_req = insn[20];
	162	wr_req = ~insn[20];
	163
	164	if(insn[20]) begin
	165	next_write_reg = 1'b1;
	166	next_write_num = insn[15:12];
	167	next_write_data = align_rddata;
	168	end
	169
	170	if(insn[21]) begin
	171	outstall = 1'b1;
	172	if(!rw_wait)
	173	next_lsr_state = 2'b10;
	174	end
a02ca509	175	end
9a0d0e43	176	2'b10: begin
a02ca509 JW	177	next_write_reg = 1'b1;
	178	next_write_num = insn[19:16];
	179	next_write_data = addr;
9a0d0e43	180	next_lsr_state = 2'b10;
a02ca509	181	end
9a0d0e43 CL	182	default: begin end
9a0d0e43 CL	183	endcase
b3bb2fb8	184	end
b3bb2fb8 CL	185	end
b3bb2fb8 CL	186	`DECODE_LDMSTM: begin
9a0d0e43 CL	187	outstall = rw_wait;
	188	next_outbubble = rw_wait;
	189	case(lsm_state)
	190	3'b001: begin
b114e03f CL	191	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
	192	/** verilator can suck my dick */
	193	next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	194	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
	195	offset = 6'b0;
9a0d0e43 CL	196	outstall = 1'b1;
9a0d0e43 CL	197	next_lsm_state = 3'b010;
e08b748a	198	end
9a0d0e43 CL	199	3'b010: begin
	200	rd_req = insn[20];
	201	wr_req = ~insn[20];
9f082c0b CL	202	casez(regs)
9f082c0b CL	203	16'b???????????????1: begin
e08b748a	204	cur_reg = 4'h0;
b114e03f	205	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	206	end
9f082c0b CL	207	16'b??????????????10: begin
e08b748a	208	cur_reg = 4'h1;
b114e03f	209	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	210	end
9f082c0b CL	211	16'b?????????????100: begin
e08b748a	212	cur_reg = 4'h2;
b114e03f	213	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	214	end
9f082c0b CL	215	16'b????????????1000: begin
e08b748a	216	cur_reg = 4'h3;
b114e03f	217	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	218	end
9f082c0b CL	219	16'b???????????10000: begin
e08b748a	220	cur_reg = 4'h4;
b114e03f	221	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	222	end
9f082c0b CL	223	16'b??????????100000: begin
e08b748a	224	cur_reg = 4'h5;
b114e03f	225	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	226	end
9f082c0b CL	227	16'b?????????1000000: begin
e08b748a	228	cur_reg = 4'h6;
b114e03f	229	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	230	end
9f082c0b CL	231	16'b????????10000000: begin
e08b748a	232	cur_reg = 4'h7;
b114e03f	233	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	234	end
9f082c0b CL	235	16'b???????100000000: begin
e08b748a	236	cur_reg = 4'h8;
b114e03f	237	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	238	end
9f082c0b CL	239	16'b??????1000000000: begin
e08b748a	240	cur_reg = 4'h9;
b114e03f	241	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	242	end
9f082c0b CL	243	16'b?????10000000000: begin
e08b748a	244	cur_reg = 4'hA;
b114e03f	245	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	246	end
9f082c0b CL	247	16'b????100000000000: begin
e08b748a	248	cur_reg = 4'hB;
b114e03f	249	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	250	end
9f082c0b CL	251	16'b???1000000000000: begin
e08b748a	252	cur_reg = 4'hC;
b114e03f	253	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	254	end
9f082c0b CL	255	16'b??10000000000000: begin
e08b748a	256	cur_reg = 4'hD;
b114e03f	257	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	258	end
9f082c0b CL	259	16'b?100000000000000: begin
e08b748a	260	cur_reg = 4'hE;
b114e03f	261	next_regs = {regs[15], 15'b0};
9f082c0b CL	262	end
9f082c0b CL	263	16'b1000000000000000: begin
e08b748a	264	cur_reg = 4'hF;
9f082c0b CL	265	next_regs = 16'b0;
	266	end
	267	default: begin
e08b748a CL	268	cur_reg = 4'hx;
e08b748a CL	269	next_regs = 16'b0;
9f082c0b CL	270	end
9f082c0b CL	271	endcase
b114e03f	272	cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
efd1aa13 CL	273	if(cur_reg == 4'hF && insn[22]) begin
	274	next_outcpsr = spsr;
	275	end
b114e03f	276
9a0d0e43 CL	277	if(rw_wait) begin
	278	next_regs = regs;
	279	cur_reg = prev_reg;
	280	raddr = prev_raddr;
	281	end
	282	else begin
	283	offset = prev_offset + 6'h4;
	284	offset_sel = insn[24] ? offset : prev_offset;
	285	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	286	if(insn[20]) begin
	287	next_write_reg = 1'b1;
	288	next_write_num = cur_reg;
	289	next_write_data = rd_data;
	290	end
b114e03f CL	291	end
	292
	293	st_read = cur_reg;
	294	wr_data = st_data;
b114e03f	295	busaddr = {raddr[31:2], 2'b0};
9a0d0e43 CL	296
	297	outstall = 1'b1;
	298
	299	if(next_regs == 16'b0) begin
	300	next_lsm_state = 3'b100;
	301	end
	302	end
	303	3'b100: begin
	304	next_write_reg = 1'b1;
	305	next_write_num = insn[19:16];
	306	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
	307	next_lsm_state = 3'b001;
b783a475	308	end
9a0d0e43 CL	309	default: begin end
9a0d0e43 CL	310	endcase
b3bb2fb8	311	end
43e4332c JW	312	`DECODE_LDCSTC: begin
	313	$display("WARNING: Unimplemented LDCSTC");
	314	end
	315	`DECODE_CDP: begin
	316	cp_req = 1;
	317	if (cp_busy) begin
	318	outstall = 1;
	319	next_outbubble = 1;
	320	end
	321	if (!cp_ack) begin
	322	/* XXX undefined instruction trap */
	323	$display("WARNING: Possible CDP undefined instruction");
	324	end
	325	end
	326	`DECODE_MRCMCR: begin
	327	cp_req = 1;
	328	cp_rnw = insn[20] /* L */;
	329	if (insn[20] == 0 /* store to coprocessor */)
	330	cp_write = op0;
	331	else begin
	332	next_write_reg = 1'b1;
	333	next_write_num = insn[15:12];
	334	next_write_data = cp_read;
	335	end
	336	if (cp_busy) begin
	337	outstall = 1;
	338	next_outbubble = 1;
	339	end
	340	if (!cp_ack) begin
	341	$display("WARNING: Possible MRCMCR undefined instruction");
	342	end
	343	end
b3bb2fb8 CL	344	default: begin end
	345	endcase
	346	end
b3bb2fb8	347	endmodule