Memory: Do not progress LSM state machine if rw_wait.
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
bb2595ed
JW
3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
b3bb2fb8
CL
21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
ab7ee9fc
JW
25 input flush,
26
b3bb2fb8
CL
27 /* bus interface */
28 output reg [31:0] busaddr,
29 output reg rd_req,
30 output reg wr_req,
31 input rw_wait,
32 output reg [31:0] wr_data,
33 input [31:0] rd_data,
9fc6c23c 34 output reg [2:0] data_size,
b3bb2fb8
CL
35
36 /* regfile interface */
37 output reg [3:0] st_read,
38 input [31:0] st_data,
a02ca509 39
979f2bd7
JW
40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
a02ca509
JW
48 /* stage inputs */
49 input inbubble,
50 input [31:0] pc,
51 input [31:0] insn,
e68b2378
JW
52 input [31:0] op0,
53 input [31:0] op1,
6d0f9d82 54 input [31:0] op2,
efd1aa13
CL
55 input [31:0] spsr,
56 input [31:0] cpsr,
fdecc897 57 input cpsrup,
a02ca509
JW
58 input write_reg,
59 input [3:0] write_num,
60 input [31:0] write_data,
b3bb2fb8 61
a02ca509
JW
62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
a02ca509
JW
66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897
JW
71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
804dc0bc
JW
81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
666ceb03
CL
87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03
CL
90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
9a0d0e43
CL
98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
6d18bf27
JW
100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
a02ca509
JW
103
104 always @(posedge clk)
105 begin
106 outpc <= pc;
107 outinsn <= insn;
c65110a8
JW
108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
95704fd3
JW
112 if (!rw_wait)
113 prev_offset <= offset;
b114e03f 114 prev_raddr <= raddr;
ab7ee9fc
JW
115 outcpsr <= next_outcpsr;
116 outspsr <= spsr;
fdecc897 117 outcpsrup <= next_outcpsrup;
9a0d0e43 118 swp_state <= next_swp_state;
666ceb03
CL
119 lsm_state <= next_lsm_state;
120 lsr_state <= next_lsr_state;
121 lsrh_state <= next_lsrh_state;
6d18bf27
JW
122 if (do_rd_data_latch)
123 rd_data_latch <= rd_data;
666ceb03 124 prevaddr <= addr;
a02ca509 125 end
d73619a2
JW
126
127 reg delayedflush = 0;
128 always @(posedge clk)
129 if (flush && outstall /* halp! I can't do it now, maybe later? */)
130 delayedflush <= 1;
131 else if (!outstall /* anything has been handled this time around */)
132 delayedflush <= 0;
bb2595ed
JW
133
134 /* Drive the state machines and stall. */
135 always @(*)
136 begin
137 outstall = 1'b0;
138 next_lsm_state = lsm_state;
139 next_lsr_state = lsr_state;
140 next_lsrh_state = lsrh_state;
141 next_swp_state = swp_state;
142 casez(insn)
143 `DECODE_ALU_SWP: if(!inbubble) begin
144 case(swp_state)
145 `SWP_READING: begin
146 outstall = 1'b1;
147 if (!rw_wait)
148 next_swp_state = `SWP_WRITING;
149 $display("SWP: read stage");
150 end
151 `SWP_WRITING: begin
152 outstall = rw_wait;
153 if(!rw_wait)
154 next_swp_state = `SWP_READING;
155 $display("SWP: write stage");
156 end
157 default: begin
158 outstall = 1'bx;
159 next_swp_state = 2'bxx;
160 end
161 endcase
162 end
163 `DECODE_ALU_MULT: begin end
164 `DECODE_ALU_HDATA_REG,
165 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
166 case(lsrh_state)
167 `LSRH_MEMIO: begin
168 outstall = rw_wait;
169 if(insn[21] | !insn[24]) begin
170 outstall = 1'b1;
171 if(!rw_wait)
172 next_lsrh_state = `LSRH_BASEWB;
173 end
174
175 if (flush) /* special case! */ begin
176 outstall = 1'b0;
177 next_lsrh_state = `LSRH_MEMIO;
178 end
179
180 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
181 end
182 `LSRH_BASEWB: begin
183 outstall = 1'b1;
184 next_lsrh_state = `LSRH_WBFLUSH;
185 end
186 `LSRH_WBFLUSH: begin
187 outstall = 1'b0;
188 next_lsrh_state = `LSRH_MEMIO;
189 end
190 default: begin
191 outstall = 1'bx;
192 next_lsrh_state = 3'bxxx;
193 end
194 endcase
195 end
196 `DECODE_LDRSTR_UNDEFINED: begin end
197 `DECODE_LDRSTR: if(!inbubble) begin
198 outstall = rw_wait;
199 case(lsr_state)
200 `LSR_MEMIO: begin
201 outstall = rw_wait;
202 next_lsr_state = `LSR_MEMIO;
203 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
204 outstall = 1'b1;
205 if (!rw_wait)
206 next_lsr_state = `LSR_STRB_WR;
207 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
208 outstall = 1'b1;
209 if (!rw_wait)
210 next_lsr_state = `LSR_BASEWB;
211 end
212
213 if (flush) begin
214 outstall = 1'b0;
215 next_lsr_state = `LSR_MEMIO;
216 end
217 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
218 end
219 `LSR_STRB_WR: begin
220 outstall = 1;
221 if(insn[21] /* W */ | !insn[24] /* P */) begin
222 if(!rw_wait)
223 next_lsr_state = `LSR_BASEWB;
224 end else if (!rw_wait)
225 next_lsr_state = `LSR_WBFLUSH;
226 $display("LDRSTR: Handling STRB");
227 end
228 `LSR_BASEWB: begin
229 outstall = 1;
230 next_lsr_state = `LSR_WBFLUSH;
231 end
232 `LSR_WBFLUSH: begin
233 outstall = 0;
234 next_lsr_state = `LSR_MEMIO;
235 end
236 default: begin
237 outstall = 1'bx;
238 next_lsr_state = 4'bxxxx;
239 end
240 endcase
241 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
242 end
243 `DECODE_LDMSTM: if(!inbubble) begin
244 outstall = rw_wait;
245 case(lsm_state)
246 `LSM_SETUP: begin
247 outstall = 1'b1;
248 next_lsm_state = `LSM_MEMIO;
249 if (flush) begin
250 outstall = 1'b0;
251 next_lsm_state = `LSM_SETUP;
252 end
253 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
254 end
255 `LSM_MEMIO: begin
256 outstall = 1'b1;
fa42d706 257 if(next_regs == 16'b0 && !rw_wait) begin
bb2595ed
JW
258 next_lsm_state = `LSM_BASEWB;
259 end
260
e92804b3 261 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, st_data, busaddr);
bb2595ed
JW
262 end
263 `LSM_BASEWB: begin
264 outstall = 1;
265 next_lsm_state = `LSM_WBFLUSH;
266 $display("LDMSTM: Stage 3: Writing back");
267 end
268 `LSM_WBFLUSH: begin
269 outstall = 0;
270 next_lsm_state = `LSM_SETUP;
271 end
272 default: begin
273 outstall = 1'bx;
274 next_lsm_state = 4'bxxxx;
275 end
276 endcase
277 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
278 end
279 `DECODE_LDCSTC: if(!inbubble) begin
280 $display("WARNING: Unimplemented LDCSTC");
281 end
282 `DECODE_CDP: if (!inbubble) begin
283 if (cp_busy) begin
284 outstall = 1;
285 end
1ce42ada
JW
286 if (!cp_ack) begin
287 /* XXX undefined instruction trap */
288 $display("WARNING: Possible CDP undefined instruction");
289 end
bb2595ed
JW
290 end
291 `DECODE_MRCMCR: if (!inbubble) begin
292 if (cp_busy) begin
293 outstall = 1;
294 end
1ce42ada
JW
295 if (!cp_ack) begin
296 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
297 end
bb2595ed
JW
298 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
299 end
300 default: begin end
301 endcase
302 end
1ce42ada
JW
303
304 /* Coprocessor input. */
305 always @(*)
306 begin
307 cp_req = 0;
308 cp_rnw = 1'bx;
309 cp_write = 32'hxxxxxxxx;
310 casez (insn)
311 `DECODE_CDP: if(!inbubble) begin
312 cp_req = 1;
313 end
314 `DECODE_MRCMCR: if(!inbubble) begin
315 cp_req = 1;
316 cp_rnw = insn[20] /* L */;
317 if (insn[20] == 0 /* store to coprocessor */)
318 cp_write = op0;
319 end
320 endcase
321 end
322
323 /* Register output logic. */
1ce42ada
JW
324 always @(*)
325 begin
326 next_write_reg = write_reg;
327 next_write_num = write_num;
328 next_write_data = write_data;
329 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
330 next_outcpsrup = cpsrup;
331
332 casez(insn)
333 `DECODE_ALU_SWP: if (!inbubble) begin
334 next_write_reg = 1'bx;
335 next_write_num = 4'bxxxx;
336 next_write_data = 32'hxxxxxxxx;
337 case(swp_state)
338 `SWP_READING:
339 next_write_reg = 1'b0;
340 `SWP_WRITING: begin
341 next_write_reg = 1'b1;
342 next_write_num = insn[15:12];
343 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
344 end
345 default: begin end
346 endcase
347 end
348 `DECODE_ALU_MULT: begin end
349 `DECODE_ALU_HDATA_REG,
350 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
351 next_write_reg = 1'bx;
352 next_write_num = 4'bxxxx;
353 next_write_data = 32'hxxxxxxxx;
354 case(lsrh_state)
355 `LSRH_MEMIO: begin
356 next_write_num = insn[15:12];
357 next_write_data = lsrh_rddata;
358 if(insn[20]) begin
359 next_write_reg = 1'b1;
360 end
361 end
362 `LSRH_BASEWB: begin
363 next_write_reg = 1'b1;
364 next_write_num = insn[19:16];
365 next_write_data = addr;
366 end
367 `LSRH_WBFLUSH:
368 next_write_reg = 1'b0;
369 default: begin end
370 endcase
371 end
372 `DECODE_LDRSTR_UNDEFINED: begin end
373 `DECODE_LDRSTR: if(!inbubble) begin
374 next_write_reg = 1'bx;
375 next_write_num = 4'bxxxx;
376 next_write_data = 32'hxxxxxxxx;
377 case(lsr_state)
378 `LSR_MEMIO: begin
379 next_write_reg = insn[20] /* L */;
380 next_write_num = insn[15:12];
381 if(insn[20] /* L */) begin
382 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
383 end
384 end
385 `LSR_STRB_WR:
386 next_write_reg = 1'b0;
387 `LSR_BASEWB: begin
388 next_write_reg = 1'b1;
389 next_write_num = insn[19:16];
390 next_write_data = addr;
391 end
392 `LSR_WBFLUSH:
393 next_write_reg = 1'b0;
394 default: begin end
395 endcase
396 end
397 `DECODE_LDMSTM: if(!inbubble) begin
398 next_write_reg = 1'bx;
399 next_write_num = 4'bxxxx;
400 next_write_data = 32'hxxxxxxxx;
401 case(lsm_state)
402 `LSM_SETUP:
403 next_write_reg = 1'b0;
404 `LSM_MEMIO: begin
fa42d706 405 if(insn[20] /* L */) begin
1ce42ada
JW
406 next_write_reg = !rw_wait;
407 next_write_num = cur_reg;
408 next_write_data = rd_data;
409 end else
410 next_write_reg = 1'b0;
411 end
412 `LSM_BASEWB: begin
413 next_write_reg = insn[21] /* writeback */;
414 next_write_num = insn[19:16];
415 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
416 if(cur_reg == 4'hF && insn[22]) begin
417 next_outcpsr = spsr;
418 next_outcpsrup = 1;
419 end
420 end
421 `LSM_WBFLUSH:
422 next_write_reg = 1'b0;
423 default: begin end
424 endcase
425 end
426 `DECODE_MRCMCR: if(!inbubble) begin
427 next_write_reg = 1'bx;
428 next_write_num = 4'bxxxx;
429 next_write_data = 32'hxxxxxxxx;
430 next_outcpsr = 32'hxxxxxxxx;
431 next_outcpsrup = 1'bx;
432 if (insn[20] == 1 /* load from coprocessor */)
433 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
434 next_write_reg = 1'b1;
435 next_write_num = insn[15:12];
436 next_write_data = cp_read;
437 end else begin
438 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
439 next_outcpsrup = 1;
440 end
441 end
442 endcase
443 end
444
50d1792c 445 /* Bus/address control logic. */
b3bb2fb8
CL
446 always @(*)
447 begin
b3bb2fb8
CL
448 rd_req = 1'b0;
449 wr_req = 1'b0;
463f8162
JW
450 offset = prev_offset;
451 addr = prevaddr;
452 raddr = 32'hxxxxxxxx;
b3bb2fb8 453 busaddr = 32'hxxxxxxxx;
2bcc55d5 454 data_size = 3'bxxx;
1ce42ada 455
d73619a2 456 casez(insn)
5989b2f5 457 `DECODE_ALU_SWP: if(!inbubble) begin
5989b2f5 458 busaddr = {op0[31:2], 2'b0};
2bcc55d5 459 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 460 case(swp_state)
33bb0152 461 `SWP_READING:
5989b2f5 462 rd_req = 1'b1;
50d1792c 463 `SWP_WRITING:
5989b2f5 464 wr_req = 1'b1;
5989b2f5
CL
465 default: begin end
466 endcase
9a0d0e43 467 end
fb529aac 468 `DECODE_ALU_MULT: begin end
666ceb03
CL
469 `DECODE_ALU_HDATA_REG,
470 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
463f8162
JW
471 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
472 raddr = insn[24] ? op0 : addr; /* pre/post increment */
666ceb03
CL
473 busaddr = raddr;
474 /* rotate to correct position */
475 case(insn[6:5])
50d1792c 476 2'b01: /* unsigned half */
2bcc55d5 477 data_size = 3'b010;
50d1792c 478 2'b10: /* signed byte */
2bcc55d5 479 data_size = 3'b001;
50d1792c 480 2'b11: /* signed half */
2bcc55d5 481 data_size = 3'b010;
ab12fa63 482 default: begin
ab12fa63 483 data_size = 3'bxxx;
ab12fa63 484 end
666ceb03 485 endcase
33bb0152 486
666ceb03 487 case(lsrh_state)
ab12fa63 488 `LSRH_MEMIO: begin
666ceb03
CL
489 rd_req = insn[20];
490 wr_req = ~insn[20];
666ceb03 491 end
33bb0152 492 `LSRH_BASEWB: begin end
1ce42ada 493 `LSRH_WBFLUSH: begin end
666ceb03
CL
494 default: begin end
495 endcase
496 end
b3bb2fb8 497 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 498 `DECODE_LDRSTR: if(!inbubble) begin
463f8162
JW
499 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
500 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 501 busaddr = raddr;
2bcc55d5 502 data_size = insn[22] ? 3'b001 : 3'b100;
33bb0152 503 case (lsr_state)
ab12fa63 504 `LSR_MEMIO: begin
6d18bf27
JW
505 rd_req = insn[20] /* L */ || insn[22] /* B */;
506 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
b3bb2fb8 507 end
50d1792c 508 `LSR_STRB_WR:
6d18bf27 509 wr_req = 1;
33bb0152
JW
510 `LSR_BASEWB: begin end
511 `LSR_WBFLUSH: begin end
512 default: begin end
513 endcase
514 end
515 `DECODE_LDMSTM: if (!inbubble) begin
516 data_size = 3'b100;
517 case (lsm_state)
463f8162
JW
518 `LSM_SETUP:
519 offset = 6'b0;
33bb0152
JW
520 `LSM_MEMIO: begin
521 rd_req = insn[20];
522 wr_req = ~insn[20];
463f8162
JW
523 offset = prev_offset + 6'h4;
524 offset_sel = insn[24] ? offset : prev_offset;
525 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
33bb0152 526 busaddr = raddr;
4d7253f1 527 end
33bb0152
JW
528 `LSM_BASEWB: begin end
529 `LSM_WBFLUSH: begin end
530 default: begin end
531 endcase
532 end
533 `DECODE_LDCSTC: begin end
534 `DECODE_CDP: begin end
535 `DECODE_MRCMCR: begin end
536 default: begin end
537 endcase
538 end
539
50d1792c 540 /* Bus data control logic. */
33bb0152
JW
541 always @(*)
542 begin
50d1792c 543 wr_data = 32'hxxxxxxxx;
33bb0152 544
33bb0152 545 casez(insn)
50d1792c
JW
546 `DECODE_ALU_SWP: if(!inbubble)
547 if (swp_state == `SWP_WRITING)
548 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
33bb0152
JW
549 `DECODE_ALU_MULT: begin end
550 `DECODE_ALU_HDATA_REG,
50d1792c 551 `DECODE_ALU_HDATA_IMM: if(!inbubble)
33bb0152 552 case(insn[6:5])
50d1792c
JW
553 2'b01: /* unsigned half */
554 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
555 2'b10: /* signed byte */
556 wr_data = {4{op2[7:0]}};
557 2'b11: /* signed half */
558 wr_data = {2{op2[15:0]}};
33bb0152
JW
559 default: begin end
560 endcase
33bb0152
JW
561 `DECODE_LDRSTR_UNDEFINED: begin end
562 `DECODE_LDRSTR: if(!inbubble) begin
50d1792c
JW
563 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
564 if (lsr_state == `LSR_STRB_WR)
565 case (busaddr[1:0])
566 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
567 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
568 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
569 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
570 endcase
b3bb2fb8 571 end
50d1792c 572 `DECODE_LDMSTM: if (!inbubble)
e92804b3 573 if (lsm_state == `LSM_MEMIO)
50d1792c
JW
574 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
575 `DECODE_LDCSTC: begin end
576 `DECODE_CDP: begin end
577 `DECODE_MRCMCR: begin end
578 default: begin end
579 endcase
580 end
581
582 /* LDM/STM register control logic. */
e54a317f 583 always @(posedge clk)
8e30fdaf 584 if (!rw_wait || lsm_state != `LSM_MEMIO)
e54a317f
JW
585 begin
586 prev_reg <= cur_reg;
587 regs <= next_regs;
588 end
589
50d1792c
JW
590 always @(*)
591 begin
e92804b3 592 st_read = 4'hx;
50d1792c
JW
593 cur_reg = prev_reg;
594 next_regs = regs;
595
596 casez(insn)
5989b2f5 597 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 598 case(lsm_state)
50d1792c 599 `LSM_SETUP:
b957d34d
JW
600 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
601 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
bb2595ed 602 `LSM_MEMIO: begin
9f082c0b
CL
603 casez(regs)
604 16'b???????????????1: begin
e08b748a 605 cur_reg = 4'h0;
b114e03f 606 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
607 end
608 16'b??????????????10: begin
e08b748a 609 cur_reg = 4'h1;
b114e03f 610 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
611 end
612 16'b?????????????100: begin
e08b748a 613 cur_reg = 4'h2;
b114e03f 614 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
615 end
616 16'b????????????1000: begin
e08b748a 617 cur_reg = 4'h3;
b114e03f 618 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
619 end
620 16'b???????????10000: begin
e08b748a 621 cur_reg = 4'h4;
b114e03f 622 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
623 end
624 16'b??????????100000: begin
e08b748a 625 cur_reg = 4'h5;
b114e03f 626 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
627 end
628 16'b?????????1000000: begin
e08b748a 629 cur_reg = 4'h6;
b114e03f 630 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
631 end
632 16'b????????10000000: begin
e08b748a 633 cur_reg = 4'h7;
b114e03f 634 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
635 end
636 16'b???????100000000: begin
e08b748a 637 cur_reg = 4'h8;
b114e03f 638 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
639 end
640 16'b??????1000000000: begin
e08b748a 641 cur_reg = 4'h9;
b114e03f 642 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
643 end
644 16'b?????10000000000: begin
e08b748a 645 cur_reg = 4'hA;
b114e03f 646 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
647 end
648 16'b????100000000000: begin
e08b748a 649 cur_reg = 4'hB;
b114e03f 650 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
651 end
652 16'b???1000000000000: begin
e08b748a 653 cur_reg = 4'hC;
b114e03f 654 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
655 end
656 16'b??10000000000000: begin
e08b748a 657 cur_reg = 4'hD;
b114e03f 658 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
659 end
660 16'b?100000000000000: begin
e08b748a 661 cur_reg = 4'hE;
b114e03f 662 next_regs = {regs[15], 15'b0};
9f082c0b
CL
663 end
664 16'b1000000000000000: begin
e08b748a 665 cur_reg = 4'hF;
9f082c0b
CL
666 next_regs = 16'b0;
667 end
668 default: begin
e08b748a
CL
669 cur_reg = 4'hx;
670 next_regs = 16'b0;
9f082c0b
CL
671 end
672 endcase
b957d34d 673 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
50d1792c 674
b114e03f 675 st_read = cur_reg;
9a0d0e43 676 end
50d1792c
JW
677 `LSM_BASEWB: begin end
678 `LSM_WBFLUSH: begin end
679 default: begin end
680 endcase
681 end
682 endcase
683 end
684
685 always @(*)
686 begin
50d1792c
JW
687 do_rd_data_latch = 0;
688
689 next_outbubble = inbubble;
690
691 lsrh_rddata = 32'hxxxxxxxx;
692 lsrh_rddata_s1 = 16'hxxxx;
693 lsrh_rddata_s2 = 8'hxx;
694 next_swp_oldval = swp_oldval;
695
696 /* XXX shit not given about endianness */
697 casez(insn)
698 `DECODE_ALU_SWP: if(!inbubble) begin
699 next_outbubble = rw_wait;
700 case(swp_state)
701 `SWP_READING:
702 if(!rw_wait)
703 next_swp_oldval = rd_data;
704 `SWP_WRITING: begin end
705 default: begin end
706 endcase
707 end
708 `DECODE_ALU_MULT: begin end
709 `DECODE_ALU_HDATA_REG,
710 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
711 next_outbubble = rw_wait;
712
713 /* rotate to correct position */
714 case(insn[6:5])
715 2'b01: begin /* unsigned half */
716 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
717 end
718 2'b10: begin /* signed byte */
719 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
720 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
721 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
722 end
723 2'b11: begin /* signed half */
724 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
725 end
726 default: begin
727 lsrh_rddata = 32'hxxxxxxxx;
728 end
729 endcase
730
731 case(lsrh_state)
732 `LSRH_MEMIO: begin end
733 `LSRH_BASEWB:
734 next_outbubble = 1'b0;
735 `LSRH_WBFLUSH: begin end
736 default: begin end
737 endcase
738 end
739 `DECODE_LDRSTR_UNDEFINED: begin end
740 `DECODE_LDRSTR: if(!inbubble) begin
741 next_outbubble = rw_wait;
742 /* rotate to correct position */
743 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
744 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
745 /* select byte or word */
746 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
747 case(lsr_state)
748 `LSR_MEMIO:
749 if (insn[22] /* B */ && !insn[20] /* L */)
750 do_rd_data_latch = 1;
751 `LSR_STRB_WR: begin end
752 `LSR_BASEWB:
753 next_outbubble = 0;
754 `LSR_WBFLUSH: begin end
755 default: begin end
756 endcase
757 end
758 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
759 `DECODE_LDMSTM: if(!inbubble) begin
760 next_outbubble = rw_wait;
761 case(lsm_state)
762 `LSM_SETUP: begin end
763 `LSM_MEMIO: begin end
1ce42ada 764 `LSM_BASEWB:
4d7253f1 765 next_outbubble = 0;
bb2595ed 766 `LSM_WBFLUSH: begin end
d73619a2 767 default: $stop;
9a0d0e43 768 endcase
43e4332c 769 end
bb2595ed 770 `DECODE_LDCSTC: begin end
5989b2f5 771 `DECODE_CDP: if(!inbubble) begin
43e4332c 772 if (cp_busy) begin
43e4332c
JW
773 next_outbubble = 1;
774 end
43e4332c 775 end
5989b2f5 776 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c 777 if (cp_busy) begin
43e4332c
JW
778 next_outbubble = 1;
779 end
43e4332c 780 end
b3bb2fb8
CL
781 default: begin end
782 endcase
d73619a2
JW
783
784 if ((flush || delayedflush) && !outstall)
785 next_outbubble = 1'b1;
b3bb2fb8 786 end
b3bb2fb8 787endmodule
This page took 0.121911 seconds and 4 git commands to generate.