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(parent: 50d1792) | patch
Memory: Only make the final latch for prev_reg and regs be gated on rw_wait.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 31 Jan 2009 10:49:31 +0000 (05:49 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 31 Jan 2009 10:49:31 +0000 (05:49 -0500)
commite54a317f08318dc016159cd7784108ca753a494f
treeb1aa3e9d1adecc8c285b0ebcf469f81909ced915tree | snapshot
parent50d1792cc6f6958c314ee3470e986ddaa4e153a5commit | diff
Memory: Only make the final latch for prev_reg and regs be gated on rw_wait.
Memory.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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