Memory: Move all state machine code out to its own always block.
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
bb2595ed
JW
3`define SWP_READING 2'b01
4`define SWP_WRITING 2'b10
5
6`define LSRH_MEMIO 3'b001
7`define LSRH_BASEWB 3'b010
8`define LSRH_WBFLUSH 3'b100
9
10`define LSR_MEMIO 4'b0001
11`define LSR_STRB_WR 4'b0010
12`define LSR_BASEWB 4'b0100
13`define LSR_WBFLUSH 4'b1000
14
15`define LSM_SETUP 4'b0001
16`define LSM_MEMIO 4'b0010
17`define LSM_BASEWB 4'b0100
18`define LSM_WBFLUSH 4'b1000
19
20
b3bb2fb8
CL
21module Memory(
22 input clk,
23 input Nrst,
b3bb2fb8 24
ab7ee9fc
JW
25 input flush,
26
b3bb2fb8
CL
27 /* bus interface */
28 output reg [31:0] busaddr,
29 output reg rd_req,
30 output reg wr_req,
31 input rw_wait,
32 output reg [31:0] wr_data,
33 input [31:0] rd_data,
9fc6c23c 34 output reg [2:0] data_size,
b3bb2fb8
CL
35
36 /* regfile interface */
37 output reg [3:0] st_read,
38 input [31:0] st_data,
a02ca509 39
979f2bd7
JW
40 /* Coprocessor interface */
41 output reg cp_req,
42 input cp_ack,
43 input cp_busy,
804dc0bc 44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
45 input [31:0] cp_read,
46 output reg [31:0] cp_write,
979f2bd7 47
a02ca509
JW
48 /* stage inputs */
49 input inbubble,
50 input [31:0] pc,
51 input [31:0] insn,
e68b2378
JW
52 input [31:0] op0,
53 input [31:0] op1,
6d0f9d82 54 input [31:0] op2,
efd1aa13
CL
55 input [31:0] spsr,
56 input [31:0] cpsr,
fdecc897 57 input cpsrup,
a02ca509
JW
58 input write_reg,
59 input [3:0] write_num,
60 input [31:0] write_data,
b3bb2fb8 61
a02ca509
JW
62 /* outputs */
63 output reg outstall,
64 output reg outbubble,
b3bb2fb8 65 output reg [31:0] outpc,
a02ca509
JW
66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc 70 output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897
JW
71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
a02ca509 73 );
b3bb2fb8 74
efd1aa13 75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897 76 reg next_outcpsrup;
666ceb03 77 reg [31:0] prevaddr;
e08b748a 78 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 79 reg next_writeback;
e08b748a 80
804dc0bc
JW
81 reg next_outbubble;
82 reg next_write_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
74d3729c 85
6d18bf27 86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
666ceb03
CL
87 reg [31:0] align_s1, align_s2, align_rddata;
88
4d7253f1 89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03
CL
90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
9a0d0e43 93
b783a475 94 reg [15:0] regs, next_regs;
4d7253f1 95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f 96 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 97
9a0d0e43
CL
98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
6d18bf27
JW
100
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
a02ca509
JW
103
104 always @(posedge clk)
105 begin
106 outpc <= pc;
107 outinsn <= insn;
c65110a8
JW
108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
e68b2378 112 regs <= next_regs;
e08b748a 113 prev_reg <= cur_reg;
95704fd3
JW
114 if (!rw_wait)
115 prev_offset <= offset;
b114e03f 116 prev_raddr <= raddr;
ab7ee9fc
JW
117 outcpsr <= next_outcpsr;
118 outspsr <= spsr;
fdecc897 119 outcpsrup <= next_outcpsrup;
9a0d0e43 120 swp_state <= next_swp_state;
666ceb03
CL
121 lsm_state <= next_lsm_state;
122 lsr_state <= next_lsr_state;
123 lsrh_state <= next_lsrh_state;
6d18bf27
JW
124 if (do_rd_data_latch)
125 rd_data_latch <= rd_data;
666ceb03 126 prevaddr <= addr;
a02ca509 127 end
d73619a2
JW
128
129 reg delayedflush = 0;
130 always @(posedge clk)
131 if (flush && outstall /* halp! I can't do it now, maybe later? */)
132 delayedflush <= 1;
133 else if (!outstall /* anything has been handled this time around */)
134 delayedflush <= 0;
bb2595ed
JW
135
136 /* Drive the state machines and stall. */
137 always @(*)
138 begin
139 outstall = 1'b0;
140 next_lsm_state = lsm_state;
141 next_lsr_state = lsr_state;
142 next_lsrh_state = lsrh_state;
143 next_swp_state = swp_state;
144 casez(insn)
145 `DECODE_ALU_SWP: if(!inbubble) begin
146 case(swp_state)
147 `SWP_READING: begin
148 outstall = 1'b1;
149 if (!rw_wait)
150 next_swp_state = `SWP_WRITING;
151 $display("SWP: read stage");
152 end
153 `SWP_WRITING: begin
154 outstall = rw_wait;
155 if(!rw_wait)
156 next_swp_state = `SWP_READING;
157 $display("SWP: write stage");
158 end
159 default: begin
160 outstall = 1'bx;
161 next_swp_state = 2'bxx;
162 end
163 endcase
164 end
165 `DECODE_ALU_MULT: begin end
166 `DECODE_ALU_HDATA_REG,
167 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
168 case(lsrh_state)
169 `LSRH_MEMIO: begin
170 outstall = rw_wait;
171 if(insn[21] | !insn[24]) begin
172 outstall = 1'b1;
173 if(!rw_wait)
174 next_lsrh_state = `LSRH_BASEWB;
175 end
176
177 if (flush) /* special case! */ begin
178 outstall = 1'b0;
179 next_lsrh_state = `LSRH_MEMIO;
180 end
181
182 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
183 end
184 `LSRH_BASEWB: begin
185 outstall = 1'b1;
186 next_lsrh_state = `LSRH_WBFLUSH;
187 end
188 `LSRH_WBFLUSH: begin
189 outstall = 1'b0;
190 next_lsrh_state = `LSRH_MEMIO;
191 end
192 default: begin
193 outstall = 1'bx;
194 next_lsrh_state = 3'bxxx;
195 end
196 endcase
197 end
198 `DECODE_LDRSTR_UNDEFINED: begin end
199 `DECODE_LDRSTR: if(!inbubble) begin
200 outstall = rw_wait;
201 case(lsr_state)
202 `LSR_MEMIO: begin
203 outstall = rw_wait;
204 next_lsr_state = `LSR_MEMIO;
205 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
206 outstall = 1'b1;
207 if (!rw_wait)
208 next_lsr_state = `LSR_STRB_WR;
209 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
210 outstall = 1'b1;
211 if (!rw_wait)
212 next_lsr_state = `LSR_BASEWB;
213 end
214
215 if (flush) begin
216 outstall = 1'b0;
217 next_lsr_state = `LSR_MEMIO;
218 end
219 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
220 end
221 `LSR_STRB_WR: begin
222 outstall = 1;
223 if(insn[21] /* W */ | !insn[24] /* P */) begin
224 if(!rw_wait)
225 next_lsr_state = `LSR_BASEWB;
226 end else if (!rw_wait)
227 next_lsr_state = `LSR_WBFLUSH;
228 $display("LDRSTR: Handling STRB");
229 end
230 `LSR_BASEWB: begin
231 outstall = 1;
232 next_lsr_state = `LSR_WBFLUSH;
233 end
234 `LSR_WBFLUSH: begin
235 outstall = 0;
236 next_lsr_state = `LSR_MEMIO;
237 end
238 default: begin
239 outstall = 1'bx;
240 next_lsr_state = 4'bxxxx;
241 end
242 endcase
243 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
244 end
245 `DECODE_LDMSTM: if(!inbubble) begin
246 outstall = rw_wait;
247 case(lsm_state)
248 `LSM_SETUP: begin
249 outstall = 1'b1;
250 next_lsm_state = `LSM_MEMIO;
251 if (flush) begin
252 outstall = 1'b0;
253 next_lsm_state = `LSM_SETUP;
254 end
255 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
256 end
257 `LSM_MEMIO: begin
258 outstall = 1'b1;
259 if(next_regs == 16'b0) begin
260 next_lsm_state = `LSM_BASEWB;
261 end
262
263 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
264 end
265 `LSM_BASEWB: begin
266 outstall = 1;
267 next_lsm_state = `LSM_WBFLUSH;
268 $display("LDMSTM: Stage 3: Writing back");
269 end
270 `LSM_WBFLUSH: begin
271 outstall = 0;
272 next_lsm_state = `LSM_SETUP;
273 end
274 default: begin
275 outstall = 1'bx;
276 next_lsm_state = 4'bxxxx;
277 end
278 endcase
279 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
280 end
281 `DECODE_LDCSTC: if(!inbubble) begin
282 $display("WARNING: Unimplemented LDCSTC");
283 end
284 `DECODE_CDP: if (!inbubble) begin
285 if (cp_busy) begin
286 outstall = 1;
287 end
288 end
289 `DECODE_MRCMCR: if (!inbubble) begin
290 if (cp_busy) begin
291 outstall = 1;
292 end
293 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
294 end
295 default: begin end
296 endcase
297 end
b3bb2fb8
CL
298
299 always @(*)
300 begin
666ceb03 301 addr = prevaddr;
b3bb2fb8
CL
302 raddr = 32'hxxxxxxxx;
303 rd_req = 1'b0;
304 wr_req = 1'b0;
305 wr_data = 32'hxxxxxxxx;
306 busaddr = 32'hxxxxxxxx;
2bcc55d5 307 data_size = 3'bxxx;
cc1ce5b3 308 st_read = 4'hx;
6d18bf27 309 do_rd_data_latch = 0;
a02ca509
JW
310 next_write_reg = write_reg;
311 next_write_num = write_num;
312 next_write_data = write_data;
c65110a8 313 next_outbubble = inbubble;
9a0d0e43 314 next_regs = regs;
979f2bd7 315 cp_req = 1'b0;
43e4332c
JW
316 cp_rnw = 1'bx;
317 cp_write = 32'hxxxxxxxx;
b114e03f 318 offset = prev_offset;
4d7253f1 319 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
fdecc897 320 next_outcpsrup = cpsrup;
666ceb03 321 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
322 lsrh_rddata_s1 = 16'hxxxx;
323 lsrh_rddata_s2 = 8'hxx;
9a0d0e43 324 next_swp_oldval = swp_oldval;
9a0d0e43 325 cur_reg = prev_reg;
9f082c0b 326
5989b2f5 327 /* XXX shit not given about endianness */
d73619a2 328 casez(insn)
5989b2f5 329 `DECODE_ALU_SWP: if(!inbubble) begin
5989b2f5
CL
330 next_outbubble = rw_wait;
331 busaddr = {op0[31:2], 2'b0};
2bcc55d5 332 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 333 case(swp_state)
ab12fa63 334 `SWP_READING: begin
5989b2f5 335 rd_req = 1'b1;
5989b2f5 336 if(!rw_wait) begin
5989b2f5 337 next_swp_oldval = rd_data;
9a0d0e43 338 end
9a0d0e43 339 end
ab12fa63 340 `SWP_WRITING: begin
5989b2f5 341 wr_req = 1'b1;
2bcc55d5 342 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
343 next_write_reg = 1'b1;
344 next_write_num = insn[15:12];
2bcc55d5 345 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5
CL
346 end
347 default: begin end
348 endcase
9a0d0e43 349 end
fb529aac 350 `DECODE_ALU_MULT: begin end
666ceb03
CL
351 `DECODE_ALU_HDATA_REG,
352 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
353 next_outbubble = rw_wait;
666ceb03
CL
354 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
355 raddr = insn[24] ? op0 : addr; /* pre/post increment */
356 busaddr = raddr;
357 /* rotate to correct position */
358 case(insn[6:5])
666ceb03
CL
359 2'b01: begin /* unsigned half */
360 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 361 data_size = 3'b010;
666ceb03
CL
362 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
363 end
364 2'b10: begin /* signed byte */
365 wr_data = {4{op2[7:0]}};
2bcc55d5 366 data_size = 3'b001;
666ceb03
CL
367 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
368 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
369 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
370 end
371 2'b11: begin /* signed half */
372 wr_data = {2{op2[15:0]}};
2bcc55d5 373 data_size = 3'b010;
666ceb03
CL
374 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
375 end
ab12fa63
JW
376 default: begin
377 wr_data = 32'hxxxxxxxx;
378 data_size = 3'bxxx;
379 lsrh_rddata = 32'hxxxxxxxx;
380 end
666ceb03
CL
381 endcase
382
383 case(lsrh_state)
ab12fa63 384 `LSRH_MEMIO: begin
666ceb03
CL
385 rd_req = insn[20];
386 wr_req = ~insn[20];
387 next_write_num = insn[15:12];
388 next_write_data = lsrh_rddata;
389 if(insn[20]) begin
390 next_write_reg = 1'b1;
391 end
666ceb03 392 end
ab12fa63 393 `LSRH_BASEWB: begin
4d7253f1 394 next_outbubble = 1'b0;
666ceb03
CL
395 next_write_reg = 1'b1;
396 next_write_num = insn[19:16];
397 next_write_data = addr;
4d7253f1 398 end
ab12fa63 399 `LSRH_WBFLUSH: begin
666ceb03
CL
400 end
401 default: begin end
402 endcase
403 end
b3bb2fb8 404 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
405 `DECODE_LDRSTR: if(!inbubble) begin
406 next_outbubble = rw_wait;
5989b2f5 407 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 408 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
409 busaddr = raddr;
410 /* rotate to correct position */
5989b2f5
CL
411 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
412 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
413 /* select byte or word */
414 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
6d18bf27 415 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
2bcc55d5 416 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 417 case(lsr_state)
ab12fa63 418 `LSR_MEMIO: begin
6d18bf27
JW
419 rd_req = insn[20] /* L */ || insn[22] /* B */;
420 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
fb529aac 421 next_write_reg = insn[20] /* L */;
666ceb03 422 next_write_num = insn[15:12];
fb529aac 423 if(insn[20] /* L */) begin
6d18bf27 424 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
a02ca509 425 end
6d18bf27
JW
426 if (insn[22] /* B */ && !insn[20] /* L */) begin
427 do_rd_data_latch = 1;
a02ca509 428 end
b3bb2fb8 429 end
ab12fa63 430 `LSR_STRB_WR: begin
6d18bf27
JW
431 rd_req = 0;
432 wr_req = 1;
433 next_write_reg = 0;
434 case (busaddr[1:0])
435 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
436 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
437 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
438 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
439 endcase
6d18bf27 440 end
ab12fa63 441 `LSR_BASEWB: begin
6d18bf27 442 rd_req = 0;
bb2595ed 443 wr_req = 0;
4d7253f1 444 next_outbubble = 0;
5989b2f5
CL
445 next_write_reg = 1'b1;
446 next_write_num = insn[19:16];
447 next_write_data = addr;
4d7253f1 448 end
ab12fa63 449 `LSR_WBFLUSH: begin
6d18bf27 450 rd_req = 0;
bb2595ed 451 wr_req = 0;
5989b2f5
CL
452 end
453 default: begin end
454 endcase
b3bb2fb8 455 end
5989b2f5
CL
456 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
457 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 458 next_outbubble = rw_wait;
2bcc55d5 459 data_size = 3'b100;
9a0d0e43 460 case(lsm_state)
ab12fa63 461 `LSM_SETUP: begin
b114e03f
CL
462// next_regs = insn[23] ? op1[15:0] : op1[0:15];
463 /** verilator can suck my dick */
b957d34d
JW
464 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
465 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 466 offset = 6'b0;
e08b748a 467 end
bb2595ed 468 `LSM_MEMIO: begin
9a0d0e43
CL
469 rd_req = insn[20];
470 wr_req = ~insn[20];
9f082c0b
CL
471 casez(regs)
472 16'b???????????????1: begin
e08b748a 473 cur_reg = 4'h0;
b114e03f 474 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
475 end
476 16'b??????????????10: begin
e08b748a 477 cur_reg = 4'h1;
b114e03f 478 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
479 end
480 16'b?????????????100: begin
e08b748a 481 cur_reg = 4'h2;
b114e03f 482 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
483 end
484 16'b????????????1000: begin
e08b748a 485 cur_reg = 4'h3;
b114e03f 486 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
487 end
488 16'b???????????10000: begin
e08b748a 489 cur_reg = 4'h4;
b114e03f 490 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
491 end
492 16'b??????????100000: begin
e08b748a 493 cur_reg = 4'h5;
b114e03f 494 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
495 end
496 16'b?????????1000000: begin
e08b748a 497 cur_reg = 4'h6;
b114e03f 498 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
499 end
500 16'b????????10000000: begin
e08b748a 501 cur_reg = 4'h7;
b114e03f 502 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
503 end
504 16'b???????100000000: begin
e08b748a 505 cur_reg = 4'h8;
b114e03f 506 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
507 end
508 16'b??????1000000000: begin
e08b748a 509 cur_reg = 4'h9;
b114e03f 510 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
511 end
512 16'b?????10000000000: begin
e08b748a 513 cur_reg = 4'hA;
b114e03f 514 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
515 end
516 16'b????100000000000: begin
e08b748a 517 cur_reg = 4'hB;
b114e03f 518 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
519 end
520 16'b???1000000000000: begin
e08b748a 521 cur_reg = 4'hC;
b114e03f 522 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
523 end
524 16'b??10000000000000: begin
e08b748a 525 cur_reg = 4'hD;
b114e03f 526 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
527 end
528 16'b?100000000000000: begin
e08b748a 529 cur_reg = 4'hE;
b114e03f 530 next_regs = {regs[15], 15'b0};
9f082c0b
CL
531 end
532 16'b1000000000000000: begin
e08b748a 533 cur_reg = 4'hF;
9f082c0b
CL
534 next_regs = 16'b0;
535 end
536 default: begin
e08b748a
CL
537 cur_reg = 4'hx;
538 next_regs = 16'b0;
9f082c0b
CL
539 end
540 endcase
b957d34d 541 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13
CL
542 if(cur_reg == 4'hF && insn[22]) begin
543 next_outcpsr = spsr;
fdecc897 544 next_outcpsrup = 1;
efd1aa13 545 end
b114e03f 546
95704fd3 547 offset = prev_offset + 6'h4;
d73619a2
JW
548 offset_sel = insn[24] ? offset : prev_offset;
549 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
550 if(insn[20]) begin
551 next_write_reg = !rw_wait;
552 next_write_num = cur_reg;
553 next_write_data = rd_data;
554 end
555 if (rw_wait) begin
556 next_regs = regs;
557 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
558 end
559
560 st_read = cur_reg;
b957d34d 561 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 562 busaddr = raddr;
9a0d0e43 563 end
ab12fa63 564 `LSM_BASEWB: begin
4d7253f1 565 next_outbubble = 0;
b957d34d 566 next_write_reg = insn[21] /* writeback */;
9a0d0e43
CL
567 next_write_num = insn[19:16];
568 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
4d7253f1 569 end
bb2595ed 570 `LSM_WBFLUSH: begin end
d73619a2 571 default: $stop;
9a0d0e43 572 endcase
43e4332c 573 end
bb2595ed 574 `DECODE_LDCSTC: begin end
5989b2f5 575 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
576 cp_req = 1;
577 if (cp_busy) begin
43e4332c
JW
578 next_outbubble = 1;
579 end
580 if (!cp_ack) begin
581 /* XXX undefined instruction trap */
582 $display("WARNING: Possible CDP undefined instruction");
583 end
584 end
5989b2f5 585 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
586 cp_req = 1;
587 cp_rnw = insn[20] /* L */;
588 if (insn[20] == 0 /* store to coprocessor */)
589 cp_write = op0;
590 else begin
d1d0eb8e
JW
591 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
592 next_write_reg = 1'b1;
593 next_write_num = insn[15:12];
594 next_write_data = cp_read;
fdecc897 595 end else begin
d1d0eb8e 596 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
fdecc897
JW
597 next_outcpsrup = 1;
598 end
43e4332c
JW
599 end
600 if (cp_busy) begin
43e4332c
JW
601 next_outbubble = 1;
602 end
603 if (!cp_ack) begin
838e283e 604 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c
JW
605 end
606 end
b3bb2fb8
CL
607 default: begin end
608 endcase
d73619a2
JW
609
610 if ((flush || delayedflush) && !outstall)
611 next_outbubble = 1'b1;
b3bb2fb8 612 end
b3bb2fb8 613endmodule
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