decode: stuff for halfword
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
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CL
6
7 /* bus interface */
8 output reg [31:0] busaddr,
9 output reg rd_req,
10 output reg wr_req,
11 input rw_wait,
12 output reg [31:0] wr_data,
13 input [31:0] rd_data,
2bcc55d5 14 output reg [2:0] data_size;
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CL
15
16 /* regfile interface */
17 output reg [3:0] st_read,
18 input [31:0] st_data,
a02ca509 19
979f2bd7
JW
20 /* Coprocessor interface */
21 output reg cp_req,
22 input cp_ack,
23 input cp_busy,
43e4332c
JW
24 output cp_rnw, /* 1 = read from CP, 0 = write to CP */
25 input [31:0] cp_read,
26 output reg [31:0] cp_write,
979f2bd7 27
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JW
28 /* stage inputs */
29 input inbubble,
30 input [31:0] pc,
31 input [31:0] insn,
e68b2378
JW
32 input [31:0] op0,
33 input [31:0] op1,
6d0f9d82 34 input [31:0] op2,
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CL
35 input [31:0] spsr,
36 input [31:0] cpsr,
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JW
37 input write_reg,
38 input [3:0] write_num,
39 input [31:0] write_data,
b3bb2fb8 40
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JW
41 /* outputs */
42 output reg outstall,
43 output reg outbubble,
b3bb2fb8 44 output reg [31:0] outpc,
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JW
45 output reg [31:0] outinsn,
46 output reg out_write_reg = 1'b0,
47 output reg [3:0] out_write_num = 4'bxxxx,
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CL
48 output reg [31:0] out_write_data = 32'hxxxxxxxx,
49 output reg [31:0] out_spsr = 32'hxxxxxxxx,
50 output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509 51 );
b3bb2fb8 52
efd1aa13 53 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
666ceb03 54 reg [31:0] prevaddr;
e08b748a 55 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 56 reg next_writeback;
e08b748a 57
c65110a8 58 wire next_outbubble;
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JW
59 wire next_write_reg;
60 wire [3:0] next_write_num;
61 wire [31:0] next_write_data;
74d3729c 62
9a0d0e43 63 reg [1:0] lsr_state = 2'b01, next_lsr_state;
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CL
64 reg [31:0] align_s1, align_s2, align_rddata;
65
66 reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
67 reg [31:0] lsrh_rddata;
68 reg [15:0] lsrh_rddata_s1;
69 reg [7:0] lsrh_rddata_s2;
9a0d0e43 70
b783a475 71 reg [15:0] regs, next_regs;
9a0d0e43 72 reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f 73 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 74
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CL
75 reg [31:0] swp_oldval, next_swp_oldval;
76 reg [1:0] swp_state = 2'b01, next_swp_state;
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77
78 always @(posedge clk)
79 begin
80 outpc <= pc;
81 outinsn <= insn;
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JW
82 outbubble <= next_outbubble;
83 out_write_reg <= next_write_reg;
84 out_write_num <= next_write_num;
85 out_write_data <= next_write_data;
e68b2378 86 regs <= next_regs;
e08b748a 87 prev_reg <= cur_reg;
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CL
88 prev_offset <= offset;
89 prev_raddr <= raddr;
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CL
90 out_cpsr <= next_outcpsr;
91 out_spsr <= spsr;
9a0d0e43 92 swp_state <= next_swp_state;
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CL
93 lsm_state <= next_lsm_state;
94 lsr_state <= next_lsr_state;
95 lsrh_state <= next_lsrh_state;
96 prevaddr <= addr;
a02ca509 97 end
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CL
98
99 always @(*)
100 begin
666ceb03 101 addr = prevaddr;
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CL
102 raddr = 32'hxxxxxxxx;
103 rd_req = 1'b0;
104 wr_req = 1'b0;
105 wr_data = 32'hxxxxxxxx;
106 busaddr = 32'hxxxxxxxx;
2bcc55d5 107 data_size = 3'bxxx;
b3bb2fb8 108 outstall = 1'b0;
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JW
109 next_write_reg = write_reg;
110 next_write_num = write_num;
111 next_write_data = write_data;
c65110a8 112 next_outbubble = inbubble;
9a0d0e43 113 next_regs = regs;
979f2bd7 114 cp_req = 1'b0;
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JW
115 cp_rnw = 1'bx;
116 cp_write = 32'hxxxxxxxx;
b114e03f 117 offset = prev_offset;
9a0d0e43 118 next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
666ceb03 119 lsrh_rddata = 32'hxxxxxxxx;
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CL
120 lsrh_rddata_s1 = 32'hxxxxxxxx;
121 lsrh_rddata_s2 = 32'hxxxxxxxx;
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CL
122 next_lsm_state = lsm_state;
123 next_lsr_state = lsr_state;
666ceb03 124 next_lsrh_state = lsrh_state;
9a0d0e43
CL
125 next_swp_oldval = swp_oldval;
126 next_swp_state = swp_state;
127 cur_reg = prev_reg;
9f082c0b 128
5989b2f5 129 /* XXX shit not given about endianness */
b3bb2fb8 130 casez(insn)
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CL
131 `DECODE_ALU_SWP: if(!inbubble) begin
132 outstall = rw_wait;
133 next_outbubble = rw_wait;
134 busaddr = {op0[31:2], 2'b0};
2bcc55d5 135 data_size = insn[22] ? 3'b001 : 3'b100;
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CL
136 case(swp_state)
137 2'b01: begin
138 rd_req = 1'b1;
139 outstall = 1'b1;
140 if(!rw_wait) begin
141 next_swp_state = 2'b10;
142 next_swp_oldval = rd_data;
9a0d0e43 143 end
9a0d0e43 144 end
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CL
145 2'b10: begin
146 wr_req = 1'b1;
2bcc55d5 147 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
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CL
148 next_write_reg = 1'b1;
149 next_write_num = insn[15:12];
2bcc55d5 150 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
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CL
151 if(!rw_wait)
152 next_swp_state = 2'b01;
153 end
154 default: begin end
155 endcase
9a0d0e43 156 end
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CL
157 `DECODE_ALU_HDATA_REG,
158 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
159 next_outbubble = rw_wait;
160 outstall = rw_wait;
161 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
162 raddr = insn[24] ? op0 : addr; /* pre/post increment */
163 busaddr = raddr;
164 /* rotate to correct position */
165 case(insn[6:5])
166 2'b00: begin end /* swp */
167 2'b01: begin /* unsigned half */
168 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 169 data_size = 3'b010;
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CL
170 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
171 end
172 2'b10: begin /* signed byte */
173 wr_data = {4{op2[7:0]}};
2bcc55d5 174 data_size = 3'b001;
666ceb03
CL
175 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
176 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
177 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
178 end
179 2'b11: begin /* signed half */
180 wr_data = {2{op2[15:0]}};
2bcc55d5 181 data_size = 3'b010;
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CL
182 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
183 end
184 endcase
185
186 case(lsrh_state)
187 2'b01: begin
188 rd_req = insn[20];
189 wr_req = ~insn[20];
190 next_write_num = insn[15:12];
191 next_write_data = lsrh_rddata;
192 if(insn[20]) begin
193 next_write_reg = 1'b1;
194 end
195 if(insn[21] | !insn[24]) begin
196 outstall = 1'b1;
197 if(!rw_wait)
198 next_lsrh_state = 2'b10;
199 end
200 end
201 2'b10: begin
202 next_write_reg = 1'b1;
203 next_write_num = insn[19:16];
204 next_write_data = addr;
205 next_lsrh_state = 2'b10;
206 end
207 default: begin end
208 endcase
209 end
b3bb2fb8 210 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
211 `DECODE_LDRSTR: if(!inbubble) begin
212 next_outbubble = rw_wait;
213 outstall = rw_wait;
214 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
215 raddr = insn[24] ? op0 : addr; /* pre/post increment */
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CL
216 busaddr = raddr;
217 /* rotate to correct position */
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CL
218 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
219 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
220 /* select byte or word */
221 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03 222 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
2bcc55d5 223 data_size = insn[22] ? 3'b001 : 3'b100;
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CL
224 case(lsr_state)
225 2'b01: begin
226 rd_req = insn[20];
227 wr_req = ~insn[20];
666ceb03
CL
228 next_write_reg = 1'b1;
229 next_write_num = insn[15:12];
5989b2f5 230 if(insn[20]) begin
5989b2f5 231 next_write_data = align_rddata;
a02ca509 232 end
666ceb03 233 if(insn[21] | !insn[24]) begin
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CL
234 outstall = 1'b1;
235 if(!rw_wait)
236 next_lsr_state = 2'b10;
a02ca509 237 end
b3bb2fb8 238 end
5989b2f5
CL
239 2'b10: begin
240 next_write_reg = 1'b1;
241 next_write_num = insn[19:16];
242 next_write_data = addr;
243 next_lsr_state = 2'b10;
244 end
245 default: begin end
246 endcase
b3bb2fb8 247 end
5989b2f5
CL
248 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
249 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43
CL
250 outstall = rw_wait;
251 next_outbubble = rw_wait;
2bcc55d5 252 data_size = 3'b100;
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CL
253 case(lsm_state)
254 3'b001: begin
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CL
255// next_regs = insn[23] ? op1[15:0] : op1[0:15];
256 /** verilator can suck my dick */
257 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
258 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
259 offset = 6'b0;
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CL
260 outstall = 1'b1;
261 next_lsm_state = 3'b010;
e08b748a 262 end
9a0d0e43
CL
263 3'b010: begin
264 rd_req = insn[20];
265 wr_req = ~insn[20];
9f082c0b
CL
266 casez(regs)
267 16'b???????????????1: begin
e08b748a 268 cur_reg = 4'h0;
b114e03f 269 next_regs = {regs[15:1], 1'b0};
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CL
270 end
271 16'b??????????????10: begin
e08b748a 272 cur_reg = 4'h1;
b114e03f 273 next_regs = {regs[15:2], 2'b0};
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CL
274 end
275 16'b?????????????100: begin
e08b748a 276 cur_reg = 4'h2;
b114e03f 277 next_regs = {regs[15:3], 3'b0};
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CL
278 end
279 16'b????????????1000: begin
e08b748a 280 cur_reg = 4'h3;
b114e03f 281 next_regs = {regs[15:4], 4'b0};
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CL
282 end
283 16'b???????????10000: begin
e08b748a 284 cur_reg = 4'h4;
b114e03f 285 next_regs = {regs[15:5], 5'b0};
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CL
286 end
287 16'b??????????100000: begin
e08b748a 288 cur_reg = 4'h5;
b114e03f 289 next_regs = {regs[15:6], 6'b0};
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CL
290 end
291 16'b?????????1000000: begin
e08b748a 292 cur_reg = 4'h6;
b114e03f 293 next_regs = {regs[15:7], 7'b0};
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CL
294 end
295 16'b????????10000000: begin
e08b748a 296 cur_reg = 4'h7;
b114e03f 297 next_regs = {regs[15:8], 8'b0};
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CL
298 end
299 16'b???????100000000: begin
e08b748a 300 cur_reg = 4'h8;
b114e03f 301 next_regs = {regs[15:9], 9'b0};
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CL
302 end
303 16'b??????1000000000: begin
e08b748a 304 cur_reg = 4'h9;
b114e03f 305 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
306 end
307 16'b?????10000000000: begin
e08b748a 308 cur_reg = 4'hA;
b114e03f 309 next_regs = {regs[15:11], 11'b0};
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CL
310 end
311 16'b????100000000000: begin
e08b748a 312 cur_reg = 4'hB;
b114e03f 313 next_regs = {regs[15:12], 12'b0};
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CL
314 end
315 16'b???1000000000000: begin
e08b748a 316 cur_reg = 4'hC;
b114e03f 317 next_regs = {regs[15:13], 13'b0};
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CL
318 end
319 16'b??10000000000000: begin
e08b748a 320 cur_reg = 4'hD;
b114e03f 321 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
322 end
323 16'b?100000000000000: begin
e08b748a 324 cur_reg = 4'hE;
b114e03f 325 next_regs = {regs[15], 15'b0};
9f082c0b
CL
326 end
327 16'b1000000000000000: begin
e08b748a 328 cur_reg = 4'hF;
9f082c0b
CL
329 next_regs = 16'b0;
330 end
331 default: begin
e08b748a
CL
332 cur_reg = 4'hx;
333 next_regs = 16'b0;
9f082c0b
CL
334 end
335 endcase
b114e03f 336 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
efd1aa13
CL
337 if(cur_reg == 4'hF && insn[22]) begin
338 next_outcpsr = spsr;
339 end
b114e03f 340
9a0d0e43
CL
341 if(rw_wait) begin
342 next_regs = regs;
343 cur_reg = prev_reg;
344 raddr = prev_raddr;
345 end
346 else begin
347 offset = prev_offset + 6'h4;
348 offset_sel = insn[24] ? offset : prev_offset;
349 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
350 if(insn[20]) begin
351 next_write_reg = 1'b1;
352 next_write_num = cur_reg;
353 next_write_data = rd_data;
354 end
b114e03f
CL
355 end
356
357 st_read = cur_reg;
358 wr_data = st_data;
666ceb03 359 busaddr = raddr;
9a0d0e43
CL
360
361 outstall = 1'b1;
362
363 if(next_regs == 16'b0) begin
364 next_lsm_state = 3'b100;
365 end
366 end
367 3'b100: begin
368 next_write_reg = 1'b1;
369 next_write_num = insn[19:16];
370 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
371 next_lsm_state = 3'b001;
b783a475 372 end
9a0d0e43
CL
373 default: begin end
374 endcase
b3bb2fb8 375 end
5989b2f5 376 `DECODE_LDCSTC: if(!inbubble) begin
43e4332c
JW
377 $display("WARNING: Unimplemented LDCSTC");
378 end
5989b2f5 379 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
380 cp_req = 1;
381 if (cp_busy) begin
382 outstall = 1;
383 next_outbubble = 1;
384 end
385 if (!cp_ack) begin
386 /* XXX undefined instruction trap */
387 $display("WARNING: Possible CDP undefined instruction");
388 end
389 end
5989b2f5 390 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
391 cp_req = 1;
392 cp_rnw = insn[20] /* L */;
393 if (insn[20] == 0 /* store to coprocessor */)
394 cp_write = op0;
395 else begin
d1d0eb8e
JW
396 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
397 next_write_reg = 1'b1;
398 next_write_num = insn[15:12];
399 next_write_data = cp_read;
400 end else
401 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c
JW
402 end
403 if (cp_busy) begin
404 outstall = 1;
405 next_outbubble = 1;
406 end
407 if (!cp_ack) begin
838e283e 408 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 409 end
838e283e 410 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 411 end
b3bb2fb8
CL
412 default: begin end
413 endcase
414 end
b3bb2fb8 415endmodule
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