[fpgaboy.git] / System.v

`timescale 1ns / 1ps

module SimROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] odata;

	reg [7:0] rom [32767:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		odata <= rom[address[10:0]];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] addrlatch = 0;
	reg romno = 0, romnotmp = 0;
	reg [7:0] brom0 [255:0];
	reg [7:0] brom1 [255:0];
	
	initial $readmemh("fpgaboot.hex", brom0);
	initial $readmemh("gbboot.hex", brom1);
	
`ifdef isim
	initial romno <= 1;
`endif

	wire decode = address[15:8] == 0;
	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		addrlatch <= address[7:0];
		if (wr && decode) romnotmp <= data[0];
		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg rdlatch = 0;
	reg [7:0] odata;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire st_nCE, st_nRST,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	parameter ADDR_PROGFLASH = 16'hFF65;
	parameter ADDR_MBC = 16'hFF64;
	
	reg rdlatch = 0, wrlatch = 0;
	reg [15:0] addrlatch = 0;
	reg [7:0] datalatch = 0;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	reg [22:0] progaddr;
	
	reg [7:0] mbc_emul = 8'b00000101;	// High bit is whether we're poking flash
						// low 7 bits are the MBC that we are emulating
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH);	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	assign st_nRST = 1;	/* Keep the strataflash out of reset. */
	assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
	
	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
	
	reg [3:0] rambank = 0;
	reg [8:0] rombank = 1;
	
	assign cr_nOE = decode ? ~rdlatch : 1;
	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
			(addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
			(addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
			((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
			23'b0;
	
	always @(posedge clk) begin
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		ADDR_PROGDATA:	if (rd || wr) begin
					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
					{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
				end
		ADDR_PROGFLASH:	if (rd || wr) begin
					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
					{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
				end
		ADDR_MBC:	begin
					mbc_emul <= data;
					rambank <= 0;
					rombank <= 1;
				end
		endcase
		
		if (mbc_emul[6:0] == 5) begin
			if ((address[15:12] == 4'h2) && wr)
				rombank <= {rombank[8], data};
			else if ((address[15:12] == 4'h3) && wr)
				rombank <= {data[0], rombank[7:0]};
			else if ((address[15:12] == 4'h4) && wr)
				rambank <= data[3:0];
		end
		
		rdlatch <= rd;
		wrlatch <= wr;
		addrlatch <= address;
		datalatch <= data;
	end
	
	assign data = (rdlatch && decode) ?
				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	input serin,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
	input ps2c, ps2d,
	output txp, txm,
	input rxp, rxm,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire serin = 1;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk, ethclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM cpudcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
	ethDCM ethdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(ethclk));
	wire [7:0] ps2buttons;
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	wire ack;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.irqack(ack),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	SimROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]),
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWE(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ),
		.st_nCE(st_nCE),
		.st_nRST(st_nRST));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));

	wire [7:0] sleds;
`ifdef isim
	assign leds = sleds;
`else
	assign leds = sleds | ps2buttons;
`endif
	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(sleds),
		.switches(switches)
		);
	
`ifdef isim
`else
	PS2Button ps2(
		.clk(clk),
		.inclk(ps2c),
		.indata(ps2d),
		.buttons(ps2buttons)
		);
`endif
	
	Buttons ass(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.int(btnirq),
	`ifdef isim
		.buttons(switches)
	`else
		.buttons(ps2buttons)
	`endif
		);

	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio),
		.serialrx(serin)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(btnirq),
		.master(irq),
		.ack(ack),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));

`ifdef isim
`else	
	Ethernet eth(
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]),
		.addr(addr[0]),
		.data(data[0]),
		.ethclk(ethclk),
		.rxclk(xtalb),
		.txp(txp),
		.txm(txm),
		.rxp(rxp),
		.rxm(rxm));
`endif
endmodule
Commit	Line	Data
a85b19a7	1	`timescale 1ns / 1ps
99b96879	2
6d070aee	3	module SimROM(
a85b19a7 JW	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
a8f4468d	9	reg rdlatch = 0;
2854e399 JW	10	reg [7:0] odata;
2854e399 JW	11
6d070aee	12	reg [7:0] rom [32767:0];
a85b19a7 JW	13	initial $readmemh("rom.hex", rom);
	14
	15	wire decode = address[15:13] == 0;
a8f4468d JW	16	always @(posedge clk) begin
a8f4468d JW	17	rdlatch <= rd && decode;
2854e399	18	odata <= rom[address[10:0]];
a8f4468d JW	19	end
a8f4468d JW	20	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 JW	21	endmodule
a85b19a7 JW	22
91c74a3f JW	23	module BootstrapROM(
	24	input [15:0] address,
	25	inout [7:0] data,
	26	input clk,
	27	input wr, rd);
	28
a8f4468d	29	reg rdlatch = 0;
e29171aa	30	reg [7:0] addrlatch = 0;
49c326da JW	31	reg romno = 0, romnotmp = 0;
	32	reg [7:0] brom0 [255:0];
	33	reg [7:0] brom1 [255:0];
	34
	35	initial $readmemh("fpgaboot.hex", brom0);
	36	initial $readmemh("gbboot.hex", brom1);
6d070aee JW	37
	38	`ifdef isim
	39	initial romno <= 1;
	40	`endif
91c74a3f JW	41
91c74a3f JW	42	wire decode = address[15:8] == 0;
49c326da	43	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa	44	always @(posedge clk) begin
a8f4468d	45	rdlatch <= rd && decode;
e29171aa	46	addrlatch <= address[7:0];
49c326da JW	47	if (wr && decode) romnotmp <= data[0];
49c326da JW	48	if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa	49	end
a8f4468d	50	assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f JW	51	endmodule
	52
	53	module MiniRAM(
6bd4619b JW	54	input [15:0] address,
	55	inout [7:0] data,
	56	input clk,
	57	input wr, rd);
	58
	59	reg [7:0] ram [127:0];
	60
	61	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d	62	reg rdlatch = 0;
6bd4619b	63	reg [7:0] odata;
a8f4468d	64	assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b	65
68ce013e	66	always @(posedge clk)
6bd4619b	67	begin
a8f4468d JW	68	rdlatch <= rd && decode;
	69	if (decode) // This has to go this way. The only way XST knows how to do
	70	begin // block ram is chip select, write enable, and always
6bd4619b JW	71	if (wr) // reading. "else if rd" does not cut it ...
	72	ram[address[6:0]] <= data;
	73	odata <= ram[address[6:0]];
	74	end
	75	end
c279b666	76	endmodule
6bd4619b	77
74610a87 JW	78	module CellularRAM(
	79	input clk,
	80	input [15:0] address,
	81	inout [7:0] data,
	82	input wr, rd,
	83	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
8e36c4ed	84	output wire st_nCE, st_nRST,
74610a87 JW	85	output wire [22:0] cr_A,
	86	inout [15:0] cr_DQ);
	87
	88	parameter ADDR_PROGADDRH = 16'hFF60;
	89	parameter ADDR_PROGADDRM = 16'hFF61;
	90	parameter ADDR_PROGADDRL = 16'hFF62;
	91	parameter ADDR_PROGDATA = 16'hFF63;
8e36c4ed	92	parameter ADDR_PROGFLASH = 16'hFF65;
6d070aee	93	parameter ADDR_MBC = 16'hFF64;
74610a87	94
a8f4468d JW	95	reg rdlatch = 0, wrlatch = 0;
	96	reg [15:0] addrlatch = 0;
	97	reg [7:0] datalatch = 0;
	98
74610a87 JW	99	reg [7:0] progaddrh, progaddrm, progaddrl;
74610a87 JW	100
1eefdc8e JW	101	reg [22:0] progaddr;
1eefdc8e JW	102
6d070aee JW	103	reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash
	104	// low 7 bits are the MBC that we are emulating
	105
74610a87	106	assign cr_nADV = 0; /* Addresses are always valid! :D */
8e36c4ed	107	assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
74610a87 JW	108	assign cr_nLB = 0; /* Lower byte is enabled */
	109	assign cr_nUB = 0; /* Upper byte is enabled */
	110	assign cr_CRE = 0; /* Data writes, not config */
	111	assign cr_CLK = 0; /* Clock? I think not! */
	112
8e36c4ed JW	113	assign st_nRST = 1; /* Keep the strataflash out of reset. */
	114	assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
	115
	116	wire decode = (addrlatch[15:14] == 2'b00) /* extrom / \|\| (addrlatch[15:13] == 3'b101) / extram */ \|\| (addrlatch == ADDR_PROGDATA) \|\| (addrlatch == ADDR_PROGFLASH);
74610a87	117
6d070aee JW	118	reg [3:0] rambank = 0;
	119	reg [8:0] rombank = 1;
	120
a8f4468d	121	assign cr_nOE = decode ? ~rdlatch : 1;
8e36c4ed	122	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) \|\| (addrlatch == ADDR_PROGFLASH) \|\| (mbc_emul[6:0] == 0) \|\| (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
74610a87	123
a8f4468d	124	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
6d070aee JW	125	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
	126	(addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
	127	(addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
8e36c4ed	128	((addrlatch == ADDR_PROGDATA) \|\| (addrlatch == ADDR_PROGFLASH)) ? progaddr :
74610a87 JW	129	23'b0;
74610a87 JW	130
a8f4468d	131	always @(posedge clk) begin
74610a87 JW	132	case (address)
	133	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	134	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	135	ADDR_PROGADDRL: if (wr) progaddrl <= data;
1eefdc8e	136	ADDR_PROGDATA: if (rd \|\| wr) begin
3db3fc27	137	progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
c231e6fb JW	138	{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
	139	end
	140	ADDR_PROGFLASH: if (rd \|\| wr) begin
	141	progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
3db3fc27	142	{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
1eefdc8e	143	end
6d070aee JW	144	ADDR_MBC: begin
	145	mbc_emul <= data;
	146	rambank <= 0;
	147	rombank <= 1;
	148	end
74610a87	149	endcase
6d070aee JW	150
	151	if (mbc_emul[6:0] == 5) begin
	152	if ((address[15:12] == 4'h2) && wr)
	153	rombank <= {rombank[8], data};
	154	else if ((address[15:12] == 4'h3) && wr)
	155	rombank <= {data[0], rombank[7:0]};
	156	else if ((address[15:12] == 4'h4) && wr)
	157	rambank <= data[3:0];
	158	end
	159
a8f4468d JW	160	rdlatch <= rd;
	161	wrlatch <= wr;
	162	addrlatch <= address;
	163	datalatch <= data;
	164	end
74610a87	165
a8f4468d JW	166	assign data = (rdlatch && decode) ?
	167	(addrlatch == ADDR_PROGADDRH) ? progaddrh :
	168	(addrlatch == ADDR_PROGADDRM) ? progaddrm :
	169	(addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87 JW	170	cr_DQ
	171	: 8'bzzzzzzzz;
	172	endmodule
	173
a85b19a7 JW	174	module InternalRAM(
	175	input [15:0] address,
	176	inout [7:0] data,
	177	input clk,
	178	input wr, rd);
	179
fe3dc890	180	// synthesis attribute ram_style of ram is block
616eebe0	181	reg [7:0] ram [8191:0];
a85b19a7	182
74610a87	183	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	184	reg [7:0] odata;
a8f4468d JW	185	reg rdlatch = 0;
a8f4468d JW	186	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	187
68ce013e	188	always @(posedge clk)
a85b19a7	189	begin
a8f4468d	190	rdlatch <= rd && decode;
74610a87 JW	191	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	192	begin // block ram is chip select, write enable, and always
95143d64	193	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	194	ram[address[12:0]] <= data;
616eebe0 JW	195	odata <= ram[address[12:0]];
c87db60a	196	end
a85b19a7 JW	197	end
	198	endmodule
	199
	200	module Switches(
	201	input [15:0] address,
	202	inout [7:0] data,
	203	input clk,
	204	input wr, rd,
	205	input [7:0] switches,
9c834ff2	206	output reg [7:0] ledout = 0);
a85b19a7 JW	207
	208	wire decode = address == 16'hFF51;
	209	reg [7:0] odata;
a8f4468d JW	210	reg rdlatch = 0;
a8f4468d JW	211	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	212
68ce013e	213	always @(posedge clk)
a85b19a7	214	begin
a8f4468d	215	rdlatch <= rd && decode;
a85b19a7 JW	216	if (decode && rd)
	217	odata <= switches;
	218	else if (decode && wr)
	219	ledout <= data;
	220	end
	221	endmodule
	222
e7fb589a JW	223	`ifdef isim
	224	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	225	endmodule
	226	`endif
	227
a85b19a7	228	module CoreTop(
e7fb589a JW	229	`ifdef isim
	230	output reg vgaclk = 0,
	231	output reg clk = 0,
	232	`else
a85b19a7 JW	233	input xtal,
a85b19a7 JW	234	input [7:0] switches,
ff7fd7f2	235	input [3:0] buttons,
a85b19a7 JW	236	output wire [7:0] leds,
a85b19a7 JW	237	output serio,
298e8085	238	input serin,
a85b19a7	239	output wire [3:0] digits,
00573fd5	240	output wire [7:0] seven,
8e36c4ed	241	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
74610a87 JW	242	output wire [22:0] cr_A,
74610a87 JW	243	inout [15:0] cr_DQ,
bc75fc67	244	input ps2c, ps2d,
99b96879	245	output txp, txm,
faa9ae6f	246	input rxp, rxm,
e7fb589a	247	`endif
00573fd5 JW	248	output wire hs, vs,
00573fd5 JW	249	output wire [2:0] r, g,
09c1936c JW	250	output wire [1:0] b,
09c1936c JW	251	output wire soundl, soundr);
e7fb589a JW	252
	253	`ifdef isim
	254	always #62 clk <= ~clk;
	255	always #100 vgaclk <= ~vgaclk;
	256
	257	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	258
e7fb589a JW	259	wire [7:0] leds;
e7fb589a JW	260	wire serio;
298e8085	261	wire serin = 1;
e7fb589a JW	262	wire [3:0] digits;
	263	wire [7:0] seven;
	264	wire [7:0] switches = 8'b0;
	265	wire [3:0] buttons = 4'b0;
	266	`else
99b96879	267	wire xtalb, clk, vgaclk, ethclk;
fe3dc890	268	IBUFG iclkbuf(.O(xtalb), .I(xtal));
99b96879	269	CPUDCM cpudcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
fe3dc890	270	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
99b96879	271	ethDCM ethdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(ethclk));
bc75fc67	272	wire [7:0] ps2buttons;
e7fb589a JW	273	`endif
e7fb589a JW	274
91c74a3f JW	275	wire [15:0] addr [1:0];
	276	wire [7:0] data [1:0];
	277	wire wr [1:0], rd [1:0];
f8db6448	278
a6b499da	279	wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
f8db6448	280	wire [7:0] jaddr;
6c46357c	281	wire [1:0] state;
d1b40456	282	wire ack;
179b4347	283
a85b19a7	284	GBZ80Core core(
179b4347	285	.clk(clk),
91c74a3f JW	286	.bus0address(addr[0]),
	287	.bus0data(data[0]),
	288	.bus0wr(wr[0]),
	289	.bus0rd(rd[0]),
	290	.bus1address(addr[1]),
	291	.bus1data(data[1]),
	292	.bus1wr(wr[1]),
	293	.bus1rd(rd[1]),
f8db6448	294	.irq(irq),
d1b40456	295	.irqack(ack),
6c46357c JW	296	.jaddr(jaddr),
6c46357c JW	297	.state(state));
a85b19a7	298
91c74a3f JW	299	BootstrapROM brom(
	300	.address(addr[1]),
	301	.data(data[1]),
	302	.clk(clk),
	303	.wr(wr[1]),
	304	.rd(rd[1]));
	305
74610a87	306	`ifdef isim
6d070aee	307	SimROM rom(
91c74a3f JW	308	.address(addr[0]),
91c74a3f JW	309	.data(data[0]),
a85b19a7	310	.clk(clk),
91c74a3f JW	311	.wr(wr[0]),
91c74a3f JW	312	.rd(rd[0]));
74610a87 JW	313	`else
	314	CellularRAM cellram(
	315	.address(addr[0]),
	316	.data(data[0]),
	317	.clk(clk),
	318	.wr(wr[0]),
7c1b9e8e	319	.rd(rd[0]),
74610a87 JW	320	.cr_nADV(cr_nADV),
	321	.cr_nCE(cr_nCE),
	322	.cr_nOE(cr_nOE),
7c1b9e8e	323	.cr_nWE(cr_nWE),
74610a87 JW	324	.cr_CRE(cr_CRE),
	325	.cr_nLB(cr_nLB),
	326	.cr_nUB(cr_nUB),
	327	.cr_CLK(cr_CLK),
	328	.cr_A(cr_A),
8e36c4ed JW	329	.cr_DQ(cr_DQ),
	330	.st_nCE(st_nCE),
	331	.st_nRST(st_nRST));
74610a87	332	`endif
a85b19a7	333
fe3dc890 JW	334	wire lcdhs, lcdvs, lcdclk;
	335	wire [2:0] lcdr, lcdg;
	336	wire [1:0] lcdb;
	337
537e1f83	338	LCDC lcdc(
537e1f83	339	.clk(clk),
91c74a3f JW	340	.addr(addr[0]),
	341	.data(data[0]),
	342	.wr(wr[0]),
	343	.rd(rd[0]),
00573fd5 JW	344	.lcdcirq(lcdcirq),
00573fd5 JW	345	.vblankirq(vblankirq),
fe3dc890 JW	346	.lcdclk(lcdclk),
	347	.lcdhs(lcdhs),
	348	.lcdvs(lcdvs),
	349	.lcdr(lcdr),
	350	.lcdg(lcdg),
	351	.lcdb(lcdb));
	352
	353	Framebuffer fb(
	354	.lcdclk(lcdclk),
	355	.lcdhs(lcdhs),
	356	.lcdvs(lcdvs),
	357	.lcdr(lcdr),
	358	.lcdg(lcdg),
	359	.lcdb(lcdb),
	360	.vgaclk(vgaclk),
00573fd5 JW	361	.vgahs(hs),
	362	.vgavs(vs),
	363	.vgar(r),
	364	.vgag(g),
	365	.vgab(b));
6d070aee	366
bc75fc67 JW	367	wire [7:0] sleds;
	368	`ifdef isim
	369	assign leds = sleds;
	370	`else
	371	assign leds = sleds \| ps2buttons;
	372	`endif
6d070aee JW	373	Switches sw(
	374	.clk(clk),
	375	.address(addr[0]),
	376	.data(data[0]),
	377	.wr(wr[0]),
	378	.rd(rd[0]),
bc75fc67	379	.ledout(sleds),
6d070aee JW	380	.switches(switches)
6d070aee JW	381	);
a6b499da	382
bc75fc67 JW	383	`ifdef isim
	384	`else
	385	PS2Button ps2(
b057a5d6	386	.clk(clk),
bc75fc67 JW	387	.inclk(ps2c),
	388	.indata(ps2d),
	389	.buttons(ps2buttons)
	390	);
	391	`endif
	392
a6b499da JW	393	Buttons ass(
	394	.core_clk(clk),
	395	.addr(addr[0]),
	396	.data(data[0]),
	397	.wr(wr[0]),
	398	.rd(rd[0]),
	399	.int(btnirq),
bc75fc67	400	`ifdef isim
a6b499da	401	.buttons(switches)
bc75fc67 JW	402	`else
	403	.buttons(ps2buttons)
	404	`endif
a6b499da	405	);
6d070aee	406
a85b19a7	407	AddrMon amon(
eb0f2fe1	408	.clk(clk),
91c74a3f	409	.addr(addr[0]),
eb0f2fe1 JW	410	.digit(digits),
eb0f2fe1 JW	411	.out(seven),
6c46357c JW	412	.freeze(buttons[0]),
6c46357c JW	413	.periods(
179b4347 JW	414	(state == 2'b00) ? 4'b0010 :
	415	(state == 2'b01) ? 4'b0001 :
	416	(state == 2'b10) ? 4'b1000 :
	417	4'b0100) );
a85b19a7	418
06ad3a30	419	UART nouart ( /* no u */
91c74a3f JW	420	.clk(clk),
	421	.addr(addr[0]),
	422	.data(data[0]),
	423	.wr(wr[0]),
	424	.rd(rd[0]),
298e8085 JW	425	.serial(serio),
298e8085 JW	426	.serialrx(serin)
eb0f2fe1	427	);
9aa931d1	428
eb0f2fe1	429	InternalRAM ram(
9aa931d1	430	.clk(clk),
91c74a3f JW	431	.address(addr[0]),
	432	.data(data[0]),
	433	.wr(wr[0]),
	434	.rd(rd[0])
eb0f2fe1	435	);
6bd4619b JW	436
6bd4619b JW	437	MiniRAM mram(
6bd4619b	438	.clk(clk),
91c74a3f JW	439	.address(addr[1]),
	440	.data(data[1]),
	441	.wr(wr[1]),
	442	.rd(rd[1])
6bd4619b	443	);
06ad3a30	444
06ad3a30 JW	445	Timer tmr(
06ad3a30 JW	446	.clk(clk),
91c74a3f JW	447	.addr(addr[0]),
	448	.data(data[0]),
	449	.wr(wr[0]),
	450	.rd(rd[0]),
eb0f2fe1 JW	451	.irq(tmrirq)
eb0f2fe1 JW	452	);
06ad3a30 JW	453
	454	Interrupt intr(
	455	.clk(clk),
91c74a3f JW	456	.addr(addr[0]),
	457	.data(data[0]),
	458	.wr(wr[0]),
	459	.rd(rd[0]),
00573fd5	460	.vblank(vblankirq),
537e1f83	461	.lcdc(lcdcirq),
06ad3a30	462	.tovf(tmrirq),
e7fb589a	463	.serial(1'b0),
a6b499da	464	.buttons(btnirq),
06ad3a30	465	.master(irq),
d1b40456	466	.ack(ack),
06ad3a30	467	.jaddr(jaddr));
09c1936c JW	468
	469	Soundcore sound(
	470	.core_clk(clk),
91c74a3f JW	471	.addr(addr[0]),
	472	.data(data[0]),
	473	.rd(rd[0]),
	474	.wr(wr[0]),
09c1936c JW	475	.snd_data_l(soundl),
09c1936c JW	476	.snd_data_r(soundr));
99b96879 JW	477
	478	`ifdef isim
	479	`else
	480	Ethernet eth(
	481	.clk(clk),
	482	.wr(wr[0]),
	483	.rd(rd[0]),
	484	.addr(addr[0]),
	485	.data(data[0]),
	486	.ethclk(ethclk),
faa9ae6f	487	.rxclk(xtalb),
99b96879	488	.txp(txp),
faa9ae6f JW	489	.txm(txm),
	490	.rxp(rxp),
	491	.rxm(rxm));
99b96879	492	`endif
a85b19a7	493	endmodule