[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] odata;

	// synthesis attribute ram_style of rom is block
	reg [7:0] rom [1023:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		odata <= rom[address[10:0]];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] addrlatch = 0;
	reg romno = 0, romnotmp = 0;
	reg [7:0] brom0 [255:0];
	reg [7:0] brom1 [255:0];
	
	initial $readmemh("fpgaboot.hex", brom0);
	initial $readmemh("gbboot.hex", brom1);

	wire decode = address[15:8] == 0;
	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		addrlatch <= address[7:0];
		if (wr && decode) romnotmp <= data[0];
		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg rdlatch = 0;
	reg [7:0] odata;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	
	reg rdlatch = 0, wrlatch = 0;
	reg [15:0] addrlatch = 0;
	reg [7:0] datalatch = 0;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = 0;	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
	
	assign cr_nOE = decode ? ~rdlatch : 1;
	assign cr_nWE = decode ? ~wrlatch : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
			(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
			(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
			23'b0;
	
	reg [7:0] regbuf;
	
	always @(posedge clk) begin
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		endcase
		rdlatch <= rd;
		wrlatch <= wr;
		addrlatch <= address;
		datalatch <= data;
	end
	
	assign data = (rdlatch && decode) ?
				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	ROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]),
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWE(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));
	
	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule
Commit	Line	Data
a85b19a7 JW	1
	2	`timescale 1ns / 1ps
	3	module ROM(
	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
a8f4468d	9	reg rdlatch = 0;
2854e399 JW	10	reg [7:0] odata;
2854e399 JW	11
91c74a3f	12	// synthesis attribute ram_style of rom is block
fe3dc890	13	reg [7:0] rom [1023:0];
a85b19a7 JW	14	initial $readmemh("rom.hex", rom);
	15
	16	wire decode = address[15:13] == 0;
a8f4468d JW	17	always @(posedge clk) begin
a8f4468d JW	18	rdlatch <= rd && decode;
2854e399	19	odata <= rom[address[10:0]];
a8f4468d JW	20	end
a8f4468d JW	21	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 JW	22	endmodule
a85b19a7 JW	23
91c74a3f JW	24	module BootstrapROM(
	25	input [15:0] address,
	26	inout [7:0] data,
	27	input clk,
	28	input wr, rd);
	29
a8f4468d	30	reg rdlatch = 0;
e29171aa	31	reg [7:0] addrlatch = 0;
49c326da JW	32	reg romno = 0, romnotmp = 0;
	33	reg [7:0] brom0 [255:0];
	34	reg [7:0] brom1 [255:0];
	35
	36	initial $readmemh("fpgaboot.hex", brom0);
	37	initial $readmemh("gbboot.hex", brom1);
91c74a3f JW	38
91c74a3f JW	39	wire decode = address[15:8] == 0;
49c326da	40	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa	41	always @(posedge clk) begin
a8f4468d	42	rdlatch <= rd && decode;
e29171aa	43	addrlatch <= address[7:0];
49c326da JW	44	if (wr && decode) romnotmp <= data[0];
49c326da JW	45	if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa	46	end
a8f4468d	47	assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f JW	48	endmodule
	49
	50	module MiniRAM(
6bd4619b JW	51	input [15:0] address,
	52	inout [7:0] data,
	53	input clk,
	54	input wr, rd);
	55
	56	reg [7:0] ram [127:0];
	57
	58	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d	59	reg rdlatch = 0;
6bd4619b	60	reg [7:0] odata;
a8f4468d	61	assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b	62
68ce013e	63	always @(posedge clk)
6bd4619b	64	begin
a8f4468d JW	65	rdlatch <= rd && decode;
	66	if (decode) // This has to go this way. The only way XST knows how to do
	67	begin // block ram is chip select, write enable, and always
6bd4619b JW	68	if (wr) // reading. "else if rd" does not cut it ...
	69	ram[address[6:0]] <= data;
	70	odata <= ram[address[6:0]];
	71	end
	72	end
c279b666	73	endmodule
6bd4619b	74
74610a87 JW	75	module CellularRAM(
	76	input clk,
	77	input [15:0] address,
	78	inout [7:0] data,
	79	input wr, rd,
	80	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	81	output wire [22:0] cr_A,
	82	inout [15:0] cr_DQ);
	83
	84	parameter ADDR_PROGADDRH = 16'hFF60;
	85	parameter ADDR_PROGADDRM = 16'hFF61;
	86	parameter ADDR_PROGADDRL = 16'hFF62;
	87	parameter ADDR_PROGDATA = 16'hFF63;
	88
a8f4468d JW	89	reg rdlatch = 0, wrlatch = 0;
	90	reg [15:0] addrlatch = 0;
	91	reg [7:0] datalatch = 0;
	92
74610a87 JW	93	reg [7:0] progaddrh, progaddrm, progaddrl;
	94
	95	assign cr_nADV = 0; /* Addresses are always valid! :D */
	96	assign cr_nCE = 0; /* The chip is enabled */
	97	assign cr_nLB = 0; /* Lower byte is enabled */
	98	assign cr_nUB = 0; /* Upper byte is enabled */
	99	assign cr_CRE = 0; /* Data writes, not config */
	100	assign cr_CLK = 0; /* Clock? I think not! */
	101
a8f4468d	102	wire decode = (addrlatch[15:14] == 2'b00) /* extrom / \|\| (addrlatch[15:13] == 3'b101) / extram */ \|\| (addrlatch == ADDR_PROGDATA);
74610a87	103
a8f4468d JW	104	assign cr_nOE = decode ? ~rdlatch : 1;
a8f4468d JW	105	assign cr_nWE = decode ? ~wrlatch : 1;
74610a87	106
a8f4468d JW	107	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	108	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
	109	(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
	110	(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
74610a87 JW	111	23'b0;
	112
	113	reg [7:0] regbuf;
	114
a8f4468d	115	always @(posedge clk) begin
74610a87 JW	116	case (address)
	117	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	118	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	119	ADDR_PROGADDRL: if (wr) progaddrl <= data;
	120	endcase
a8f4468d JW	121	rdlatch <= rd;
	122	wrlatch <= wr;
	123	addrlatch <= address;
	124	datalatch <= data;
	125	end
74610a87	126
a8f4468d JW	127	assign data = (rdlatch && decode) ?
	128	(addrlatch == ADDR_PROGADDRH) ? progaddrh :
	129	(addrlatch == ADDR_PROGADDRM) ? progaddrm :
	130	(addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87 JW	131	cr_DQ
	132	: 8'bzzzzzzzz;
	133	endmodule
	134
a85b19a7 JW	135	module InternalRAM(
	136	input [15:0] address,
	137	inout [7:0] data,
	138	input clk,
	139	input wr, rd);
	140
fe3dc890	141	// synthesis attribute ram_style of ram is block
616eebe0	142	reg [7:0] ram [8191:0];
a85b19a7	143
74610a87	144	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	145	reg [7:0] odata;
a8f4468d JW	146	reg rdlatch = 0;
a8f4468d JW	147	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	148
68ce013e	149	always @(posedge clk)
a85b19a7	150	begin
a8f4468d	151	rdlatch <= rd && decode;
74610a87 JW	152	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	153	begin // block ram is chip select, write enable, and always
95143d64	154	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	155	ram[address[12:0]] <= data;
616eebe0 JW	156	odata <= ram[address[12:0]];
c87db60a	157	end
a85b19a7 JW	158	end
	159	endmodule
	160
	161	module Switches(
	162	input [15:0] address,
	163	inout [7:0] data,
	164	input clk,
	165	input wr, rd,
	166	input [7:0] switches,
9c834ff2	167	output reg [7:0] ledout = 0);
a85b19a7 JW	168
	169	wire decode = address == 16'hFF51;
	170	reg [7:0] odata;
a8f4468d JW	171	reg rdlatch = 0;
a8f4468d JW	172	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	173
68ce013e	174	always @(posedge clk)
a85b19a7	175	begin
a8f4468d	176	rdlatch <= rd && decode;
a85b19a7 JW	177	if (decode && rd)
	178	odata <= switches;
	179	else if (decode && wr)
	180	ledout <= data;
	181	end
	182	endmodule
	183
e7fb589a JW	184	`ifdef isim
	185	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	186	endmodule
	187	`endif
	188
a85b19a7	189	module CoreTop(
e7fb589a JW	190	`ifdef isim
	191	output reg vgaclk = 0,
	192	output reg clk = 0,
	193	`else
a85b19a7 JW	194	input xtal,
a85b19a7 JW	195	input [7:0] switches,
ff7fd7f2	196	input [3:0] buttons,
a85b19a7 JW	197	output wire [7:0] leds,
	198	output serio,
	199	output wire [3:0] digits,
00573fd5	200	output wire [7:0] seven,
74610a87 JW	201	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	202	output wire [22:0] cr_A,
	203	inout [15:0] cr_DQ,
e7fb589a	204	`endif
00573fd5 JW	205	output wire hs, vs,
00573fd5 JW	206	output wire [2:0] r, g,
09c1936c JW	207	output wire [1:0] b,
09c1936c JW	208	output wire soundl, soundr);
e7fb589a JW	209
	210	`ifdef isim
	211	always #62 clk <= ~clk;
	212	always #100 vgaclk <= ~vgaclk;
	213
	214	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	215
e7fb589a JW	216	wire [7:0] leds;
	217	wire serio;
	218	wire [3:0] digits;
	219	wire [7:0] seven;
	220	wire [7:0] switches = 8'b0;
	221	wire [3:0] buttons = 4'b0;
	222	`else
fe3dc890 JW	223	wire xtalb, clk, vgaclk;
	224	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	225	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	226	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	227	`endif
e7fb589a JW	228
91c74a3f JW	229	wire [15:0] addr [1:0];
	230	wire [7:0] data [1:0];
	231	wire wr [1:0], rd [1:0];
f8db6448	232
00573fd5	233	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	234	wire [7:0] jaddr;
6c46357c	235	wire [1:0] state;
179b4347	236
a85b19a7	237	GBZ80Core core(
179b4347	238	.clk(clk),
91c74a3f JW	239	.bus0address(addr[0]),
	240	.bus0data(data[0]),
	241	.bus0wr(wr[0]),
	242	.bus0rd(rd[0]),
	243	.bus1address(addr[1]),
	244	.bus1data(data[1]),
	245	.bus1wr(wr[1]),
	246	.bus1rd(rd[1]),
f8db6448	247	.irq(irq),
6c46357c JW	248	.jaddr(jaddr),
6c46357c JW	249	.state(state));
a85b19a7	250
91c74a3f JW	251	BootstrapROM brom(
	252	.address(addr[1]),
	253	.data(data[1]),
	254	.clk(clk),
	255	.wr(wr[1]),
	256	.rd(rd[1]));
	257
74610a87	258	`ifdef isim
a85b19a7	259	ROM rom(
91c74a3f JW	260	.address(addr[0]),
91c74a3f JW	261	.data(data[0]),
a85b19a7	262	.clk(clk),
91c74a3f JW	263	.wr(wr[0]),
91c74a3f JW	264	.rd(rd[0]));
74610a87 JW	265	`else
	266	CellularRAM cellram(
	267	.address(addr[0]),
	268	.data(data[0]),
	269	.clk(clk),
	270	.wr(wr[0]),
7c1b9e8e	271	.rd(rd[0]),
74610a87 JW	272	.cr_nADV(cr_nADV),
	273	.cr_nCE(cr_nCE),
	274	.cr_nOE(cr_nOE),
7c1b9e8e	275	.cr_nWE(cr_nWE),
74610a87 JW	276	.cr_CRE(cr_CRE),
	277	.cr_nLB(cr_nLB),
	278	.cr_nUB(cr_nUB),
	279	.cr_CLK(cr_CLK),
	280	.cr_A(cr_A),
	281	.cr_DQ(cr_DQ));
	282	`endif
a85b19a7	283
fe3dc890 JW	284	wire lcdhs, lcdvs, lcdclk;
	285	wire [2:0] lcdr, lcdg;
	286	wire [1:0] lcdb;
	287
537e1f83	288	LCDC lcdc(
537e1f83	289	.clk(clk),
91c74a3f JW	290	.addr(addr[0]),
	291	.data(data[0]),
	292	.wr(wr[0]),
	293	.rd(rd[0]),
00573fd5 JW	294	.lcdcirq(lcdcirq),
00573fd5 JW	295	.vblankirq(vblankirq),
fe3dc890 JW	296	.lcdclk(lcdclk),
	297	.lcdhs(lcdhs),
	298	.lcdvs(lcdvs),
	299	.lcdr(lcdr),
	300	.lcdg(lcdg),
	301	.lcdb(lcdb));
	302
	303	Framebuffer fb(
	304	.lcdclk(lcdclk),
	305	.lcdhs(lcdhs),
	306	.lcdvs(lcdvs),
	307	.lcdr(lcdr),
	308	.lcdg(lcdg),
	309	.lcdb(lcdb),
	310	.vgaclk(vgaclk),
00573fd5 JW	311	.vgahs(hs),
	312	.vgavs(vs),
	313	.vgar(r),
	314	.vgag(g),
	315	.vgab(b));
537e1f83	316
a85b19a7	317	AddrMon amon(
eb0f2fe1	318	.clk(clk),
91c74a3f	319	.addr(addr[0]),
eb0f2fe1 JW	320	.digit(digits),
eb0f2fe1 JW	321	.out(seven),
6c46357c JW	322	.freeze(buttons[0]),
6c46357c JW	323	.periods(
179b4347 JW	324	(state == 2'b00) ? 4'b0010 :
	325	(state == 2'b01) ? 4'b0001 :
	326	(state == 2'b10) ? 4'b1000 :
	327	4'b0100) );
a85b19a7 JW	328
a85b19a7 JW	329	Switches sw(
a85b19a7	330	.clk(clk),
91c74a3f JW	331	.address(addr[0]),
	332	.data(data[0]),
	333	.wr(wr[0]),
	334	.rd(rd[0]),
a85b19a7	335	.ledout(leds),
fc443a4f	336	.switches(switches)
a85b19a7 JW	337	);
a85b19a7 JW	338
06ad3a30	339	UART nouart ( /* no u */
91c74a3f JW	340	.clk(clk),
	341	.addr(addr[0]),
	342	.data(data[0]),
	343	.wr(wr[0]),
	344	.rd(rd[0]),
eb0f2fe1 JW	345	.serial(serio)
eb0f2fe1 JW	346	);
9aa931d1	347
eb0f2fe1	348	InternalRAM ram(
9aa931d1	349	.clk(clk),
91c74a3f JW	350	.address(addr[0]),
	351	.data(data[0]),
	352	.wr(wr[0]),
	353	.rd(rd[0])
eb0f2fe1	354	);
6bd4619b JW	355
6bd4619b JW	356	MiniRAM mram(
6bd4619b	357	.clk(clk),
91c74a3f JW	358	.address(addr[1]),
	359	.data(data[1]),
	360	.wr(wr[1]),
	361	.rd(rd[1])
6bd4619b	362	);
06ad3a30	363
06ad3a30 JW	364	Timer tmr(
06ad3a30 JW	365	.clk(clk),
91c74a3f JW	366	.addr(addr[0]),
	367	.data(data[0]),
	368	.wr(wr[0]),
	369	.rd(rd[0]),
eb0f2fe1 JW	370	.irq(tmrirq)
eb0f2fe1 JW	371	);
06ad3a30 JW	372
	373	Interrupt intr(
	374	.clk(clk),
91c74a3f JW	375	.addr(addr[0]),
	376	.data(data[0]),
	377	.wr(wr[0]),
	378	.rd(rd[0]),
00573fd5	379	.vblank(vblankirq),
537e1f83	380	.lcdc(lcdcirq),
06ad3a30	381	.tovf(tmrirq),
e7fb589a JW	382	.serial(1'b0),
e7fb589a JW	383	.buttons(1'b0),
06ad3a30 JW	384	.master(irq),
06ad3a30 JW	385	.jaddr(jaddr));
09c1936c JW	386
	387	Soundcore sound(
	388	.core_clk(clk),
91c74a3f JW	389	.addr(addr[0]),
	390	.data(data[0]),
	391	.rd(rd[0]),
	392	.wr(wr[0]),
09c1936c JW	393	.snd_data_l(soundl),
09c1936c JW	394	.snd_data_r(soundr));
a85b19a7	395	endmodule