Dual boot ROM support, and the first proof that cellular ram works!
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
a8f4468d 9 reg rdlatch = 0;
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10 reg [7:0] odata;
11
91c74a3f 12 // synthesis attribute ram_style of rom is block
fe3dc890 13 reg [7:0] rom [1023:0];
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14 initial $readmemh("rom.hex", rom);
15
16 wire decode = address[15:13] == 0;
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17 always @(posedge clk) begin
18 rdlatch <= rd && decode;
2854e399 19 odata <= rom[address[10:0]];
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20 end
21 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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22endmodule
23
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24module BootstrapROM(
25 input [15:0] address,
26 inout [7:0] data,
27 input clk,
28 input wr, rd);
29
a8f4468d 30 reg rdlatch = 0;
e29171aa 31 reg [7:0] addrlatch = 0;
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32 reg romno = 0, romnotmp = 0;
33 reg [7:0] brom0 [255:0];
34 reg [7:0] brom1 [255:0];
35
36 initial $readmemh("fpgaboot.hex", brom0);
37 initial $readmemh("gbboot.hex", brom1);
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38
39 wire decode = address[15:8] == 0;
49c326da 40 wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa 41 always @(posedge clk) begin
a8f4468d 42 rdlatch <= rd && decode;
e29171aa 43 addrlatch <= address[7:0];
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44 if (wr && decode) romnotmp <= data[0];
45 if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa 46 end
a8f4468d 47 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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48endmodule
49
50module MiniRAM(
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51 input [15:0] address,
52 inout [7:0] data,
53 input clk,
54 input wr, rd);
55
56 reg [7:0] ram [127:0];
57
58 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d 59 reg rdlatch = 0;
6bd4619b 60 reg [7:0] odata;
a8f4468d 61 assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b 62
68ce013e 63 always @(posedge clk)
6bd4619b 64 begin
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65 rdlatch <= rd && decode;
66 if (decode) // This has to go this way. The only way XST knows how to do
67 begin // block ram is chip select, write enable, and always
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68 if (wr) // reading. "else if rd" does not cut it ...
69 ram[address[6:0]] <= data;
70 odata <= ram[address[6:0]];
71 end
72 end
c279b666 73endmodule
6bd4619b 74
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75module CellularRAM(
76 input clk,
77 input [15:0] address,
78 inout [7:0] data,
79 input wr, rd,
80 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
81 output wire [22:0] cr_A,
82 inout [15:0] cr_DQ);
83
84 parameter ADDR_PROGADDRH = 16'hFF60;
85 parameter ADDR_PROGADDRM = 16'hFF61;
86 parameter ADDR_PROGADDRL = 16'hFF62;
87 parameter ADDR_PROGDATA = 16'hFF63;
88
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89 reg rdlatch = 0, wrlatch = 0;
90 reg [15:0] addrlatch = 0;
91 reg [7:0] datalatch = 0;
92
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93 reg [7:0] progaddrh, progaddrm, progaddrl;
94
95 assign cr_nADV = 0; /* Addresses are always valid! :D */
96 assign cr_nCE = 0; /* The chip is enabled */
97 assign cr_nLB = 0; /* Lower byte is enabled */
98 assign cr_nUB = 0; /* Upper byte is enabled */
99 assign cr_CRE = 0; /* Data writes, not config */
100 assign cr_CLK = 0; /* Clock? I think not! */
101
a8f4468d 102 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
74610a87 103
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104 assign cr_nOE = decode ? ~rdlatch : 1;
105 assign cr_nWE = decode ? ~wrlatch : 1;
74610a87 106
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107 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
108 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
109 (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
110 (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
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111 23'b0;
112
113 reg [7:0] regbuf;
114
a8f4468d 115 always @(posedge clk) begin
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116 case (address)
117 ADDR_PROGADDRH: if (wr) progaddrh <= data;
118 ADDR_PROGADDRM: if (wr) progaddrm <= data;
119 ADDR_PROGADDRL: if (wr) progaddrl <= data;
120 endcase
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121 rdlatch <= rd;
122 wrlatch <= wr;
123 addrlatch <= address;
124 datalatch <= data;
125 end
74610a87 126
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127 assign data = (rdlatch && decode) ?
128 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
129 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
130 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
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131 cr_DQ
132 : 8'bzzzzzzzz;
133endmodule
134
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135module InternalRAM(
136 input [15:0] address,
137 inout [7:0] data,
138 input clk,
139 input wr, rd);
140
fe3dc890 141 // synthesis attribute ram_style of ram is block
616eebe0 142 reg [7:0] ram [8191:0];
a85b19a7 143
74610a87 144 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7 145 reg [7:0] odata;
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146 reg rdlatch = 0;
147 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 148
68ce013e 149 always @(posedge clk)
a85b19a7 150 begin
a8f4468d 151 rdlatch <= rd && decode;
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152 if (decode) // This has to go this way. The only way XST knows how to do
153 begin // block ram is chip select, write enable, and always
95143d64 154 if (wr) // reading. "else if rd" does not cut it ...
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155 ram[address[12:0]] <= data;
156 odata <= ram[address[12:0]];
c87db60a 157 end
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158 end
159endmodule
160
161module Switches(
162 input [15:0] address,
163 inout [7:0] data,
164 input clk,
165 input wr, rd,
166 input [7:0] switches,
9c834ff2 167 output reg [7:0] ledout = 0);
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168
169 wire decode = address == 16'hFF51;
170 reg [7:0] odata;
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171 reg rdlatch = 0;
172 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 173
68ce013e 174 always @(posedge clk)
a85b19a7 175 begin
a8f4468d 176 rdlatch <= rd && decode;
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177 if (decode && rd)
178 odata <= switches;
179 else if (decode && wr)
180 ledout <= data;
181 end
182endmodule
183
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184`ifdef isim
185module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
186endmodule
187`endif
188
a85b19a7 189module CoreTop(
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190`ifdef isim
191 output reg vgaclk = 0,
192 output reg clk = 0,
193`else
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194 input xtal,
195 input [7:0] switches,
ff7fd7f2 196 input [3:0] buttons,
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197 output wire [7:0] leds,
198 output serio,
199 output wire [3:0] digits,
00573fd5 200 output wire [7:0] seven,
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201 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
202 output wire [22:0] cr_A,
203 inout [15:0] cr_DQ,
e7fb589a 204`endif
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205 output wire hs, vs,
206 output wire [2:0] r, g,
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207 output wire [1:0] b,
208 output wire soundl, soundr);
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209
210`ifdef isim
211 always #62 clk <= ~clk;
212 always #100 vgaclk <= ~vgaclk;
213
214 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 215
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216 wire [7:0] leds;
217 wire serio;
218 wire [3:0] digits;
219 wire [7:0] seven;
220 wire [7:0] switches = 8'b0;
221 wire [3:0] buttons = 4'b0;
222`else
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223 wire xtalb, clk, vgaclk;
224 IBUFG iclkbuf(.O(xtalb), .I(xtal));
225 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
226 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
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227`endif
228
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229 wire [15:0] addr [1:0];
230 wire [7:0] data [1:0];
231 wire wr [1:0], rd [1:0];
f8db6448 232
00573fd5 233 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 234 wire [7:0] jaddr;
6c46357c 235 wire [1:0] state;
179b4347 236
a85b19a7 237 GBZ80Core core(
179b4347 238 .clk(clk),
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239 .bus0address(addr[0]),
240 .bus0data(data[0]),
241 .bus0wr(wr[0]),
242 .bus0rd(rd[0]),
243 .bus1address(addr[1]),
244 .bus1data(data[1]),
245 .bus1wr(wr[1]),
246 .bus1rd(rd[1]),
f8db6448 247 .irq(irq),
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248 .jaddr(jaddr),
249 .state(state));
a85b19a7 250
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251 BootstrapROM brom(
252 .address(addr[1]),
253 .data(data[1]),
254 .clk(clk),
255 .wr(wr[1]),
256 .rd(rd[1]));
257
74610a87 258`ifdef isim
a85b19a7 259 ROM rom(
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260 .address(addr[0]),
261 .data(data[0]),
a85b19a7 262 .clk(clk),
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263 .wr(wr[0]),
264 .rd(rd[0]));
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265`else
266 CellularRAM cellram(
267 .address(addr[0]),
268 .data(data[0]),
269 .clk(clk),
270 .wr(wr[0]),
7c1b9e8e 271 .rd(rd[0]),
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272 .cr_nADV(cr_nADV),
273 .cr_nCE(cr_nCE),
274 .cr_nOE(cr_nOE),
7c1b9e8e 275 .cr_nWE(cr_nWE),
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276 .cr_CRE(cr_CRE),
277 .cr_nLB(cr_nLB),
278 .cr_nUB(cr_nUB),
279 .cr_CLK(cr_CLK),
280 .cr_A(cr_A),
281 .cr_DQ(cr_DQ));
282`endif
a85b19a7 283
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284 wire lcdhs, lcdvs, lcdclk;
285 wire [2:0] lcdr, lcdg;
286 wire [1:0] lcdb;
287
537e1f83 288 LCDC lcdc(
537e1f83 289 .clk(clk),
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290 .addr(addr[0]),
291 .data(data[0]),
292 .wr(wr[0]),
293 .rd(rd[0]),
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294 .lcdcirq(lcdcirq),
295 .vblankirq(vblankirq),
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296 .lcdclk(lcdclk),
297 .lcdhs(lcdhs),
298 .lcdvs(lcdvs),
299 .lcdr(lcdr),
300 .lcdg(lcdg),
301 .lcdb(lcdb));
302
303 Framebuffer fb(
304 .lcdclk(lcdclk),
305 .lcdhs(lcdhs),
306 .lcdvs(lcdvs),
307 .lcdr(lcdr),
308 .lcdg(lcdg),
309 .lcdb(lcdb),
310 .vgaclk(vgaclk),
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311 .vgahs(hs),
312 .vgavs(vs),
313 .vgar(r),
314 .vgag(g),
315 .vgab(b));
537e1f83 316
a85b19a7 317 AddrMon amon(
eb0f2fe1 318 .clk(clk),
91c74a3f 319 .addr(addr[0]),
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320 .digit(digits),
321 .out(seven),
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322 .freeze(buttons[0]),
323 .periods(
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324 (state == 2'b00) ? 4'b0010 :
325 (state == 2'b01) ? 4'b0001 :
326 (state == 2'b10) ? 4'b1000 :
327 4'b0100) );
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328
329 Switches sw(
a85b19a7 330 .clk(clk),
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331 .address(addr[0]),
332 .data(data[0]),
333 .wr(wr[0]),
334 .rd(rd[0]),
a85b19a7 335 .ledout(leds),
fc443a4f 336 .switches(switches)
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337 );
338
06ad3a30 339 UART nouart ( /* no u */
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340 .clk(clk),
341 .addr(addr[0]),
342 .data(data[0]),
343 .wr(wr[0]),
344 .rd(rd[0]),
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345 .serial(serio)
346 );
9aa931d1 347
eb0f2fe1 348 InternalRAM ram(
9aa931d1 349 .clk(clk),
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350 .address(addr[0]),
351 .data(data[0]),
352 .wr(wr[0]),
353 .rd(rd[0])
eb0f2fe1 354 );
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355
356 MiniRAM mram(
6bd4619b 357 .clk(clk),
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358 .address(addr[1]),
359 .data(data[1]),
360 .wr(wr[1]),
361 .rd(rd[1])
6bd4619b 362 );
06ad3a30 363
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364 Timer tmr(
365 .clk(clk),
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366 .addr(addr[0]),
367 .data(data[0]),
368 .wr(wr[0]),
369 .rd(rd[0]),
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370 .irq(tmrirq)
371 );
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372
373 Interrupt intr(
374 .clk(clk),
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375 .addr(addr[0]),
376 .data(data[0]),
377 .wr(wr[0]),
378 .rd(rd[0]),
00573fd5 379 .vblank(vblankirq),
537e1f83 380 .lcdc(lcdcirq),
06ad3a30 381 .tovf(tmrirq),
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382 .serial(1'b0),
383 .buttons(1'b0),
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384 .master(irq),
385 .jaddr(jaddr));
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386
387 Soundcore sound(
388 .core_clk(clk),
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389 .addr(addr[0]),
390 .data(data[0]),
391 .rd(rd[0]),
392 .wr(wr[0]),
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393 .snd_data_l(soundl),
394 .snd_data_r(soundr));
a85b19a7 395endmodule
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