Make binwire a little bit more error-resistant
[fpgaboy.git] / System.v
CommitLineData
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1
2`timescale 1ns / 1ps
6d070aee 3module SimROM(
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4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
a8f4468d 9 reg rdlatch = 0;
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10 reg [7:0] odata;
11
6d070aee 12 reg [7:0] rom [32767:0];
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13 initial $readmemh("rom.hex", rom);
14
15 wire decode = address[15:13] == 0;
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16 always @(posedge clk) begin
17 rdlatch <= rd && decode;
2854e399 18 odata <= rom[address[10:0]];
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19 end
20 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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21endmodule
22
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23module BootstrapROM(
24 input [15:0] address,
25 inout [7:0] data,
26 input clk,
27 input wr, rd);
28
a8f4468d 29 reg rdlatch = 0;
e29171aa 30 reg [7:0] addrlatch = 0;
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31 reg romno = 0, romnotmp = 0;
32 reg [7:0] brom0 [255:0];
33 reg [7:0] brom1 [255:0];
34
35 initial $readmemh("fpgaboot.hex", brom0);
36 initial $readmemh("gbboot.hex", brom1);
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37
38`ifdef isim
39 initial romno <= 1;
40`endif
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41
42 wire decode = address[15:8] == 0;
49c326da 43 wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa 44 always @(posedge clk) begin
a8f4468d 45 rdlatch <= rd && decode;
e29171aa 46 addrlatch <= address[7:0];
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47 if (wr && decode) romnotmp <= data[0];
48 if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa 49 end
a8f4468d 50 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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51endmodule
52
53module MiniRAM(
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54 input [15:0] address,
55 inout [7:0] data,
56 input clk,
57 input wr, rd);
58
59 reg [7:0] ram [127:0];
60
61 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d 62 reg rdlatch = 0;
6bd4619b 63 reg [7:0] odata;
a8f4468d 64 assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b 65
68ce013e 66 always @(posedge clk)
6bd4619b 67 begin
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68 rdlatch <= rd && decode;
69 if (decode) // This has to go this way. The only way XST knows how to do
70 begin // block ram is chip select, write enable, and always
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71 if (wr) // reading. "else if rd" does not cut it ...
72 ram[address[6:0]] <= data;
73 odata <= ram[address[6:0]];
74 end
75 end
c279b666 76endmodule
6bd4619b 77
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78module CellularRAM(
79 input clk,
80 input [15:0] address,
81 inout [7:0] data,
82 input wr, rd,
83 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
84 output wire [22:0] cr_A,
85 inout [15:0] cr_DQ);
86
87 parameter ADDR_PROGADDRH = 16'hFF60;
88 parameter ADDR_PROGADDRM = 16'hFF61;
89 parameter ADDR_PROGADDRL = 16'hFF62;
90 parameter ADDR_PROGDATA = 16'hFF63;
6d070aee 91 parameter ADDR_MBC = 16'hFF64;
74610a87 92
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93 reg rdlatch = 0, wrlatch = 0;
94 reg [15:0] addrlatch = 0;
95 reg [7:0] datalatch = 0;
96
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97 reg [7:0] progaddrh, progaddrm, progaddrl;
98
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99 reg [22:0] progaddr;
100
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101 reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash
102 // low 7 bits are the MBC that we are emulating
103
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104 assign cr_nADV = 0; /* Addresses are always valid! :D */
105 assign cr_nCE = 0; /* The chip is enabled */
106 assign cr_nLB = 0; /* Lower byte is enabled */
107 assign cr_nUB = 0; /* Upper byte is enabled */
108 assign cr_CRE = 0; /* Data writes, not config */
109 assign cr_CLK = 0; /* Clock? I think not! */
110
a8f4468d 111 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
74610a87 112
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113 reg [3:0] rambank = 0;
114 reg [8:0] rombank = 1;
115
a8f4468d 116 assign cr_nOE = decode ? ~rdlatch : 1;
6d070aee 117 assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
74610a87 118
a8f4468d 119 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
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120 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
121 (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
122 (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
123 (addrlatch == ADDR_PROGDATA) ? progaddr :
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124 23'b0;
125
a8f4468d 126 always @(posedge clk) begin
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127 case (address)
128 ADDR_PROGADDRH: if (wr) progaddrh <= data;
129 ADDR_PROGADDRM: if (wr) progaddrm <= data;
130 ADDR_PROGADDRL: if (wr) progaddrl <= data;
1eefdc8e 131 ADDR_PROGDATA: if (rd || wr) begin
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132 progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
133 {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
1eefdc8e 134 end
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135 ADDR_MBC: begin
136 mbc_emul <= data;
137 rambank <= 0;
138 rombank <= 1;
139 end
74610a87 140 endcase
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141
142 if (mbc_emul[6:0] == 5) begin
143 if ((address[15:12] == 4'h2) && wr)
144 rombank <= {rombank[8], data};
145 else if ((address[15:12] == 4'h3) && wr)
146 rombank <= {data[0], rombank[7:0]};
147 else if ((address[15:12] == 4'h4) && wr)
148 rambank <= data[3:0];
149 end
150
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151 rdlatch <= rd;
152 wrlatch <= wr;
153 addrlatch <= address;
154 datalatch <= data;
155 end
74610a87 156
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157 assign data = (rdlatch && decode) ?
158 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
159 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
160 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
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161 cr_DQ
162 : 8'bzzzzzzzz;
163endmodule
164
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165module InternalRAM(
166 input [15:0] address,
167 inout [7:0] data,
168 input clk,
169 input wr, rd);
170
fe3dc890 171 // synthesis attribute ram_style of ram is block
616eebe0 172 reg [7:0] ram [8191:0];
a85b19a7 173
74610a87 174 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7 175 reg [7:0] odata;
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176 reg rdlatch = 0;
177 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 178
68ce013e 179 always @(posedge clk)
a85b19a7 180 begin
a8f4468d 181 rdlatch <= rd && decode;
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182 if (decode) // This has to go this way. The only way XST knows how to do
183 begin // block ram is chip select, write enable, and always
95143d64 184 if (wr) // reading. "else if rd" does not cut it ...
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185 ram[address[12:0]] <= data;
186 odata <= ram[address[12:0]];
c87db60a 187 end
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188 end
189endmodule
190
191module Switches(
192 input [15:0] address,
193 inout [7:0] data,
194 input clk,
195 input wr, rd,
196 input [7:0] switches,
9c834ff2 197 output reg [7:0] ledout = 0);
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198
199 wire decode = address == 16'hFF51;
200 reg [7:0] odata;
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201 reg rdlatch = 0;
202 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 203
68ce013e 204 always @(posedge clk)
a85b19a7 205 begin
a8f4468d 206 rdlatch <= rd && decode;
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207 if (decode && rd)
208 odata <= switches;
209 else if (decode && wr)
210 ledout <= data;
211 end
212endmodule
213
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214`ifdef isim
215module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
216endmodule
217`endif
218
a85b19a7 219module CoreTop(
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220`ifdef isim
221 output reg vgaclk = 0,
222 output reg clk = 0,
223`else
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224 input xtal,
225 input [7:0] switches,
ff7fd7f2 226 input [3:0] buttons,
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227 output wire [7:0] leds,
228 output serio,
298e8085 229 input serin,
a85b19a7 230 output wire [3:0] digits,
00573fd5 231 output wire [7:0] seven,
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232 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
233 output wire [22:0] cr_A,
234 inout [15:0] cr_DQ,
e7fb589a 235`endif
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236 output wire hs, vs,
237 output wire [2:0] r, g,
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238 output wire [1:0] b,
239 output wire soundl, soundr);
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240
241`ifdef isim
242 always #62 clk <= ~clk;
243 always #100 vgaclk <= ~vgaclk;
244
245 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 246
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247 wire [7:0] leds;
248 wire serio;
298e8085 249 wire serin = 1;
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250 wire [3:0] digits;
251 wire [7:0] seven;
252 wire [7:0] switches = 8'b0;
253 wire [3:0] buttons = 4'b0;
254`else
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255 wire xtalb, clk, vgaclk;
256 IBUFG iclkbuf(.O(xtalb), .I(xtal));
257 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
258 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
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259`endif
260
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261 wire [15:0] addr [1:0];
262 wire [7:0] data [1:0];
263 wire wr [1:0], rd [1:0];
f8db6448 264
00573fd5 265 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 266 wire [7:0] jaddr;
6c46357c 267 wire [1:0] state;
179b4347 268
a85b19a7 269 GBZ80Core core(
179b4347 270 .clk(clk),
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271 .bus0address(addr[0]),
272 .bus0data(data[0]),
273 .bus0wr(wr[0]),
274 .bus0rd(rd[0]),
275 .bus1address(addr[1]),
276 .bus1data(data[1]),
277 .bus1wr(wr[1]),
278 .bus1rd(rd[1]),
f8db6448 279 .irq(irq),
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280 .jaddr(jaddr),
281 .state(state));
a85b19a7 282
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283 BootstrapROM brom(
284 .address(addr[1]),
285 .data(data[1]),
286 .clk(clk),
287 .wr(wr[1]),
288 .rd(rd[1]));
289
74610a87 290`ifdef isim
6d070aee 291 SimROM rom(
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292 .address(addr[0]),
293 .data(data[0]),
a85b19a7 294 .clk(clk),
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295 .wr(wr[0]),
296 .rd(rd[0]));
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297`else
298 CellularRAM cellram(
299 .address(addr[0]),
300 .data(data[0]),
301 .clk(clk),
302 .wr(wr[0]),
7c1b9e8e 303 .rd(rd[0]),
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304 .cr_nADV(cr_nADV),
305 .cr_nCE(cr_nCE),
306 .cr_nOE(cr_nOE),
7c1b9e8e 307 .cr_nWE(cr_nWE),
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308 .cr_CRE(cr_CRE),
309 .cr_nLB(cr_nLB),
310 .cr_nUB(cr_nUB),
311 .cr_CLK(cr_CLK),
312 .cr_A(cr_A),
313 .cr_DQ(cr_DQ));
314`endif
a85b19a7 315
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316 wire lcdhs, lcdvs, lcdclk;
317 wire [2:0] lcdr, lcdg;
318 wire [1:0] lcdb;
319
537e1f83 320 LCDC lcdc(
537e1f83 321 .clk(clk),
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322 .addr(addr[0]),
323 .data(data[0]),
324 .wr(wr[0]),
325 .rd(rd[0]),
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326 .lcdcirq(lcdcirq),
327 .vblankirq(vblankirq),
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328 .lcdclk(lcdclk),
329 .lcdhs(lcdhs),
330 .lcdvs(lcdvs),
331 .lcdr(lcdr),
332 .lcdg(lcdg),
333 .lcdb(lcdb));
334
335 Framebuffer fb(
336 .lcdclk(lcdclk),
337 .lcdhs(lcdhs),
338 .lcdvs(lcdvs),
339 .lcdr(lcdr),
340 .lcdg(lcdg),
341 .lcdb(lcdb),
342 .vgaclk(vgaclk),
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343 .vgahs(hs),
344 .vgavs(vs),
345 .vgar(r),
346 .vgag(g),
347 .vgab(b));
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348
349 Switches sw(
350 .clk(clk),
351 .address(addr[0]),
352 .data(data[0]),
353 .wr(wr[0]),
354 .rd(rd[0]),
355 .ledout(leds),
356 .switches(switches)
357 );
358
a85b19a7 359 AddrMon amon(
eb0f2fe1 360 .clk(clk),
91c74a3f 361 .addr(addr[0]),
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362 .digit(digits),
363 .out(seven),
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364 .freeze(buttons[0]),
365 .periods(
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366 (state == 2'b00) ? 4'b0010 :
367 (state == 2'b01) ? 4'b0001 :
368 (state == 2'b10) ? 4'b1000 :
369 4'b0100) );
a85b19a7 370
06ad3a30 371 UART nouart ( /* no u */
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372 .clk(clk),
373 .addr(addr[0]),
374 .data(data[0]),
375 .wr(wr[0]),
376 .rd(rd[0]),
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377 .serial(serio),
378 .serialrx(serin)
eb0f2fe1 379 );
9aa931d1 380
eb0f2fe1 381 InternalRAM ram(
9aa931d1 382 .clk(clk),
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383 .address(addr[0]),
384 .data(data[0]),
385 .wr(wr[0]),
386 .rd(rd[0])
eb0f2fe1 387 );
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388
389 MiniRAM mram(
6bd4619b 390 .clk(clk),
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391 .address(addr[1]),
392 .data(data[1]),
393 .wr(wr[1]),
394 .rd(rd[1])
6bd4619b 395 );
06ad3a30 396
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397 Timer tmr(
398 .clk(clk),
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399 .addr(addr[0]),
400 .data(data[0]),
401 .wr(wr[0]),
402 .rd(rd[0]),
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403 .irq(tmrirq)
404 );
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405
406 Interrupt intr(
407 .clk(clk),
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408 .addr(addr[0]),
409 .data(data[0]),
410 .wr(wr[0]),
411 .rd(rd[0]),
00573fd5 412 .vblank(vblankirq),
537e1f83 413 .lcdc(lcdcirq),
06ad3a30 414 .tovf(tmrirq),
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415 .serial(1'b0),
416 .buttons(1'b0),
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417 .master(irq),
418 .jaddr(jaddr));
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419
420 Soundcore sound(
421 .core_clk(clk),
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422 .addr(addr[0]),
423 .data(data[0]),
424 .rd(rd[0]),
425 .wr(wr[0]),
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426 .snd_data_l(soundl),
427 .snd_data_r(soundr));
a85b19a7 428endmodule
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