Add files, and add a freezeswitch to debug this issue with push no type check.
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] ram [8191:0];
25
9aa931d1 26 wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
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27 reg [7:0] odata;
28 wire idata = data;
29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
33 if (decode && rd)
34 odata <= ram[address[12:0]];
35 else if (decode && wr)
36 ram[address[12:0]] <= data;
37 end
38endmodule
39
40module Switches(
41 input [15:0] address,
42 inout [7:0] data,
43 input clk,
44 input wr, rd,
45 input [7:0] switches,
46 output reg [7:0] ledout);
47
48 wire decode = address == 16'hFF51;
49 reg [7:0] odata;
50 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
51
52 always @(negedge clk)
53 begin
54 if (decode && rd)
55 odata <= switches;
56 else if (decode && wr)
57 ledout <= data;
58 end
59endmodule
60
61module CoreTop(
62 input xtal,
63 input [7:0] switches,
ff7fd7f2 64 input [3:0] buttons,
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65 output wire [7:0] leds,
66 output serio,
67 output wire [3:0] digits,
68 output wire [7:0] seven);
69
70 wire clk;
71 //IBUFG ibuf (.O(clk), .I(iclk));
72
73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
74
75 wire [15:0] addr;
76 wire [7:0] data;
77 wire wr, rd;
78
79 GBZ80Core core(
80 .clk(clk),
81 .busaddress(addr),
82 .busdata(data),
83 .buswr(wr),
84 .busrd(rd));
85
86 ROM rom(
87 .address(addr),
88 .data(data),
89 .clk(clk),
90 .wr(wr),
91 .rd(rd));
92
93 AddrMon amon(
94 .addr(addr),
95 .clk(clk),
96 .digit(digits),
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97 .out(seven),
98 .freeze(buttons[0])
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99 );
100
101 Switches sw(
102 .address(addr),
103 .data(data),
104 .clk(clk),
105 .wr(wr),
106 .rd(rd),
107 .ledout(leds),
108 .switches(switches)
109 );
110
111 UART nouart (
112 .clk(clk),
113 .wr(wr),
114 .rd(rd),
115 .addr(addr),
116 .data(data),
117 .serial(serio)
118 );
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119
120 InternalRAM ram(
121 .address(addr),
122 .data(data),
123 .clk(clk),
124 .wr(wr),
125 .rd(rd));
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126endmodule
127
128module TestBench();
129 reg clk = 0;
130 wire [15:0] addr;
131 wire [7:0] data;
132 wire wr, rd;
133
134// wire [7:0] leds;
135// wire [7:0] switches;
136
137 always #10 clk <= ~clk;
138 GBZ80Core core(
139 .clk(clk),
140 .busaddress(addr),
141 .busdata(data),
142 .buswr(wr),
143 .busrd(rd));
144
145 ROM rom(
146 .clk(clk),
147 .address(addr),
148 .data(data),
149 .wr(wr),
150 .rd(rd));
151
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152 InternalRAM ram(
153 .address(addr),
154 .data(data),
155 .clk(clk),
156 .wr(wr),
157 .rd(rd));
a85b19a7 158
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159 wire serio;
160 UART uart(
161 .addr(addr),
162 .data(data),
163 .clk(clk),
164 .wr(wr),
165 .rd(rd),
166 .serial(serio));
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167
168// Switches sw(
169// .clk(clk),
170// .address(addr),
171// .data(data),
172// .wr(wr),
173// .rd(rd),
174// .switches(switches),
175// .leds(leds));
176endmodule
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