[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg [7:0] odata;

	// synthesis attribute ram_style of rom is block
	reg [7:0] rom [1023:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk)
		odata <= rom[address[10:0]];
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg [7:0] brom [255:0];
	initial $readmemh("bootstrap.hex", brom);

	wire decode = address[15:8] == 0;
	wire [7:0] odata = brom[address[7:0]];
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		if (decode)	// This has to go this way. The only way XST knows how to do
		begin				// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = 0;	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	wire decode = (address[15:14] == 2'b00) /* extrom */ || (address[15:13] == 3'b101) /* extram */ || (address == ADDR_PROGDATA);
	
	assign cr_nOE = decode ? ~rd : 1;
	assign cr_nWE = decode ? ~wr : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, data};
	assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
			(address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
			(address == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
			23'b0;
	
	reg [7:0] regbuf;
	
	always @(posedge clk)
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		endcase
	
	assign data = (rd && decode) ?
				(address == ADDR_PROGADDRH) ? progaddrh :
				(address == ADDR_PROGADDRM) ? progaddrm :
				(address == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	ROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0])
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWR(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));
	
	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule
Commit	Line	Data
a85b19a7 JW	1
	2	`timescale 1ns / 1ps
	3	module ROM(
	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
2854e399 JW	9	reg [7:0] odata;
2854e399 JW	10
91c74a3f	11	// synthesis attribute ram_style of rom is block
fe3dc890	12	reg [7:0] rom [1023:0];
a85b19a7 JW	13	initial $readmemh("rom.hex", rom);
	14
	15	wire decode = address[15:13] == 0;
2854e399 JW	16	always @(posedge clk)
2854e399 JW	17	odata <= rom[address[10:0]];
a85b19a7	18	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
a85b19a7 JW	19	endmodule
a85b19a7 JW	20
91c74a3f JW	21	module BootstrapROM(
	22	input [15:0] address,
	23	inout [7:0] data,
	24	input clk,
	25	input wr, rd);
	26
2854e399 JW	27	reg [7:0] brom [255:0];
2854e399 JW	28	initial $readmemh("bootstrap.hex", brom);
91c74a3f JW	29
91c74a3f JW	30	wire decode = address[15:8] == 0;
2854e399	31	wire [7:0] odata = brom[address[7:0]];
91c74a3f JW	32	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	33	endmodule
	34
	35	module MiniRAM(
6bd4619b JW	36	input [15:0] address,
	37	inout [7:0] data,
	38	input clk,
	39	input wr, rd);
	40
	41	reg [7:0] ram [127:0];
	42
	43	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	44	reg [7:0] odata;
	45	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	46
68ce013e	47	always @(posedge clk)
6bd4619b JW	48	begin
	49	if (decode) // This has to go this way. The only way XST knows how to do
	50	begin // block ram is chip select, write enable, and always
	51	if (wr) // reading. "else if rd" does not cut it ...
	52	ram[address[6:0]] <= data;
	53	odata <= ram[address[6:0]];
	54	end
	55	end
c279b666	56	endmodule
6bd4619b	57
74610a87 JW	58	module CellularRAM(
	59	input clk,
	60	input [15:0] address,
	61	inout [7:0] data,
	62	input wr, rd,
	63	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	64	output wire [22:0] cr_A,
	65	inout [15:0] cr_DQ);
	66
	67	parameter ADDR_PROGADDRH = 16'hFF60;
	68	parameter ADDR_PROGADDRM = 16'hFF61;
	69	parameter ADDR_PROGADDRL = 16'hFF62;
	70	parameter ADDR_PROGDATA = 16'hFF63;
	71
	72	reg [7:0] progaddrh, progaddrm, progaddrl;
	73
	74	assign cr_nADV = 0; /* Addresses are always valid! :D */
	75	assign cr_nCE = 0; /* The chip is enabled */
	76	assign cr_nLB = 0; /* Lower byte is enabled */
	77	assign cr_nUB = 0; /* Upper byte is enabled */
	78	assign cr_CRE = 0; /* Data writes, not config */
	79	assign cr_CLK = 0; /* Clock? I think not! */
	80
	81	wire decode = (address[15:14] == 2'b00) /* extrom / \|\| (address[15:13] == 3'b101) / extram */ \|\| (address == ADDR_PROGDATA);
	82
	83	assign cr_nOE = decode ? ~rd : 1;
	84	assign cr_nWE = decode ? ~wr : 1;
	85
	86	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, data};
	87	assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
	88	(address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
	89	(address == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
	90	23'b0;
	91
	92	reg [7:0] regbuf;
	93
	94	always @(posedge clk)
	95	case (address)
	96	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	97	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	98	ADDR_PROGADDRL: if (wr) progaddrl <= data;
	99	endcase
	100
	101	assign data = (rd && decode) ?
	102	(address == ADDR_PROGADDRH) ? progaddrh :
	103	(address == ADDR_PROGADDRM) ? progaddrm :
	104	(address == ADDR_PROGADDRL) ? progaddrl :
	105	cr_DQ
	106	: 8'bzzzzzzzz;
	107	endmodule
	108
a85b19a7 JW	109	module InternalRAM(
	110	input [15:0] address,
	111	inout [7:0] data,
	112	input clk,
	113	input wr, rd);
	114
fe3dc890	115	// synthesis attribute ram_style of ram is block
616eebe0	116	reg [7:0] ram [8191:0];
a85b19a7	117
74610a87	118	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	119	reg [7:0] odata;
a85b19a7 JW	120	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
a85b19a7 JW	121
68ce013e	122	always @(posedge clk)
a85b19a7	123	begin
74610a87 JW	124	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	125	begin // block ram is chip select, write enable, and always
95143d64	126	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	127	ram[address[12:0]] <= data;
616eebe0 JW	128	odata <= ram[address[12:0]];
c87db60a	129	end
a85b19a7 JW	130	end
	131	endmodule
	132
	133	module Switches(
	134	input [15:0] address,
	135	inout [7:0] data,
	136	input clk,
	137	input wr, rd,
	138	input [7:0] switches,
9c834ff2	139	output reg [7:0] ledout = 0);
a85b19a7 JW	140
	141	wire decode = address == 16'hFF51;
	142	reg [7:0] odata;
	143	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	144
68ce013e	145	always @(posedge clk)
a85b19a7 JW	146	begin
	147	if (decode && rd)
	148	odata <= switches;
	149	else if (decode && wr)
	150	ledout <= data;
	151	end
	152	endmodule
	153
e7fb589a JW	154	`ifdef isim
	155	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	156	endmodule
	157	`endif
	158
a85b19a7	159	module CoreTop(
e7fb589a JW	160	`ifdef isim
	161	output reg vgaclk = 0,
	162	output reg clk = 0,
	163	`else
a85b19a7 JW	164	input xtal,
a85b19a7 JW	165	input [7:0] switches,
ff7fd7f2	166	input [3:0] buttons,
a85b19a7 JW	167	output wire [7:0] leds,
	168	output serio,
	169	output wire [3:0] digits,
00573fd5	170	output wire [7:0] seven,
74610a87 JW	171	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	172	output wire [22:0] cr_A,
	173	inout [15:0] cr_DQ,
e7fb589a	174	`endif
00573fd5 JW	175	output wire hs, vs,
00573fd5 JW	176	output wire [2:0] r, g,
09c1936c JW	177	output wire [1:0] b,
09c1936c JW	178	output wire soundl, soundr);
e7fb589a JW	179
	180	`ifdef isim
	181	always #62 clk <= ~clk;
	182	always #100 vgaclk <= ~vgaclk;
	183
	184	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	185
e7fb589a JW	186	wire [7:0] leds;
	187	wire serio;
	188	wire [3:0] digits;
	189	wire [7:0] seven;
	190	wire [7:0] switches = 8'b0;
	191	wire [3:0] buttons = 4'b0;
	192	`else
fe3dc890 JW	193	wire xtalb, clk, vgaclk;
	194	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	195	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	196	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	197	`endif
e7fb589a JW	198
91c74a3f JW	199	wire [15:0] addr [1:0];
	200	wire [7:0] data [1:0];
	201	wire wr [1:0], rd [1:0];
f8db6448	202
00573fd5	203	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	204	wire [7:0] jaddr;
6c46357c	205	wire [1:0] state;
179b4347	206
a85b19a7	207	GBZ80Core core(
179b4347	208	.clk(clk),
91c74a3f JW	209	.bus0address(addr[0]),
	210	.bus0data(data[0]),
	211	.bus0wr(wr[0]),
	212	.bus0rd(rd[0]),
	213	.bus1address(addr[1]),
	214	.bus1data(data[1]),
	215	.bus1wr(wr[1]),
	216	.bus1rd(rd[1]),
f8db6448	217	.irq(irq),
6c46357c JW	218	.jaddr(jaddr),
6c46357c JW	219	.state(state));
a85b19a7	220
91c74a3f JW	221	BootstrapROM brom(
	222	.address(addr[1]),
	223	.data(data[1]),
	224	.clk(clk),
	225	.wr(wr[1]),
	226	.rd(rd[1]));
	227
74610a87	228	`ifdef isim
a85b19a7	229	ROM rom(
91c74a3f JW	230	.address(addr[0]),
91c74a3f JW	231	.data(data[0]),
a85b19a7	232	.clk(clk),
91c74a3f JW	233	.wr(wr[0]),
91c74a3f JW	234	.rd(rd[0]));
74610a87 JW	235	`else
	236	CellularRAM cellram(
	237	.address(addr[0]),
	238	.data(data[0]),
	239	.clk(clk),
	240	.wr(wr[0]),
	241	.rd(rd[0])
	242	.cr_nADV(cr_nADV),
	243	.cr_nCE(cr_nCE),
	244	.cr_nOE(cr_nOE),
	245	.cr_nWR(cr_nWE),
	246	.cr_CRE(cr_CRE),
	247	.cr_nLB(cr_nLB),
	248	.cr_nUB(cr_nUB),
	249	.cr_CLK(cr_CLK),
	250	.cr_A(cr_A),
	251	.cr_DQ(cr_DQ));
	252	`endif
a85b19a7	253
fe3dc890 JW	254	wire lcdhs, lcdvs, lcdclk;
	255	wire [2:0] lcdr, lcdg;
	256	wire [1:0] lcdb;
	257
537e1f83	258	LCDC lcdc(
537e1f83	259	.clk(clk),
91c74a3f JW	260	.addr(addr[0]),
	261	.data(data[0]),
	262	.wr(wr[0]),
	263	.rd(rd[0]),
00573fd5 JW	264	.lcdcirq(lcdcirq),
00573fd5 JW	265	.vblankirq(vblankirq),
fe3dc890 JW	266	.lcdclk(lcdclk),
	267	.lcdhs(lcdhs),
	268	.lcdvs(lcdvs),
	269	.lcdr(lcdr),
	270	.lcdg(lcdg),
	271	.lcdb(lcdb));
	272
	273	Framebuffer fb(
	274	.lcdclk(lcdclk),
	275	.lcdhs(lcdhs),
	276	.lcdvs(lcdvs),
	277	.lcdr(lcdr),
	278	.lcdg(lcdg),
	279	.lcdb(lcdb),
	280	.vgaclk(vgaclk),
00573fd5 JW	281	.vgahs(hs),
	282	.vgavs(vs),
	283	.vgar(r),
	284	.vgag(g),
	285	.vgab(b));
537e1f83	286
a85b19a7	287	AddrMon amon(
eb0f2fe1	288	.clk(clk),
91c74a3f	289	.addr(addr[0]),
eb0f2fe1 JW	290	.digit(digits),
eb0f2fe1 JW	291	.out(seven),
6c46357c JW	292	.freeze(buttons[0]),
6c46357c JW	293	.periods(
179b4347 JW	294	(state == 2'b00) ? 4'b0010 :
	295	(state == 2'b01) ? 4'b0001 :
	296	(state == 2'b10) ? 4'b1000 :
	297	4'b0100) );
a85b19a7 JW	298
a85b19a7 JW	299	Switches sw(
a85b19a7	300	.clk(clk),
91c74a3f JW	301	.address(addr[0]),
	302	.data(data[0]),
	303	.wr(wr[0]),
	304	.rd(rd[0]),
a85b19a7	305	.ledout(leds),
fc443a4f	306	.switches(switches)
a85b19a7 JW	307	);
a85b19a7 JW	308
06ad3a30	309	UART nouart ( /* no u */
91c74a3f JW	310	.clk(clk),
	311	.addr(addr[0]),
	312	.data(data[0]),
	313	.wr(wr[0]),
	314	.rd(rd[0]),
eb0f2fe1 JW	315	.serial(serio)
eb0f2fe1 JW	316	);
9aa931d1	317
eb0f2fe1	318	InternalRAM ram(
9aa931d1	319	.clk(clk),
91c74a3f JW	320	.address(addr[0]),
	321	.data(data[0]),
	322	.wr(wr[0]),
	323	.rd(rd[0])
eb0f2fe1	324	);
6bd4619b JW	325
6bd4619b JW	326	MiniRAM mram(
6bd4619b	327	.clk(clk),
91c74a3f JW	328	.address(addr[1]),
	329	.data(data[1]),
	330	.wr(wr[1]),
	331	.rd(rd[1])
6bd4619b	332	);
06ad3a30	333
06ad3a30 JW	334	Timer tmr(
06ad3a30 JW	335	.clk(clk),
91c74a3f JW	336	.addr(addr[0]),
	337	.data(data[0]),
	338	.wr(wr[0]),
	339	.rd(rd[0]),
eb0f2fe1 JW	340	.irq(tmrirq)
eb0f2fe1 JW	341	);
06ad3a30 JW	342
	343	Interrupt intr(
	344	.clk(clk),
91c74a3f JW	345	.addr(addr[0]),
	346	.data(data[0]),
	347	.wr(wr[0]),
	348	.rd(rd[0]),
00573fd5	349	.vblank(vblankirq),
537e1f83	350	.lcdc(lcdcirq),
06ad3a30	351	.tovf(tmrirq),
e7fb589a JW	352	.serial(1'b0),
e7fb589a JW	353	.buttons(1'b0),
06ad3a30 JW	354	.master(irq),
06ad3a30 JW	355	.jaddr(jaddr));
09c1936c JW	356
	357	Soundcore sound(
	358	.core_clk(clk),
91c74a3f JW	359	.addr(addr[0]),
	360	.data(data[0]),
	361	.rd(rd[0]),
	362	.wr(wr[0]),
09c1936c JW	363	.snd_data_l(soundl),
09c1936c JW	364	.snd_data_r(soundr));
a85b19a7	365	endmodule