PUSH bugfix
[fpgaboy.git] / System.v
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a85b19a7
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
a85b19a7 28 reg [7:0] odata;
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29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
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33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
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36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
c87db60a 38 end
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39 end
40endmodule
41
42module Switches(
43 input [15:0] address,
44 inout [7:0] data,
45 input clk,
46 input wr, rd,
47 input [7:0] switches,
9c834ff2 48 output reg [7:0] ledout = 0);
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49
50 wire decode = address == 16'hFF51;
51 reg [7:0] odata;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
56 if (decode && rd)
57 odata <= switches;
58 else if (decode && wr)
59 ledout <= data;
60 end
61endmodule
62
63module CoreTop(
64 input xtal,
65 input [7:0] switches,
ff7fd7f2 66 input [3:0] buttons,
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67 output wire [7:0] leds,
68 output serio,
69 output wire [3:0] digits,
70 output wire [7:0] seven);
71
06ad3a30 72 wire clk;
a85b19a7 73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
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74
75 wire cclk;
76 IBUFG ibuf (.O(cclk), .I(switches[0]));
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77
78 wire [15:0] addr;
79 wire [7:0] data;
80 wire wr, rd;
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81
82 wire irq, tmrirq;
83 wire [7:0] jaddr;
6c46357c 84 wire [1:0] state;
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85
86 GBZ80Core core(
6c46357c 87 .clk(cclk),
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88 .busaddress(addr),
89 .busdata(data),
90 .buswr(wr),
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91 .busrd(rd),
92 .irq(irq),
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93 .jaddr(jaddr),
94 .state(state));
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95
96 ROM rom(
97 .address(addr),
98 .data(data),
99 .clk(clk),
100 .wr(wr),
101 .rd(rd));
102
103 AddrMon amon(
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104 .addr(addr),
105 .clk(clk),
106 .digit(digits),
107 .out(seven),
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108 .freeze(buttons[0]),
109 .periods(
110 (state == 2'b00) ? 4'b1000 :
111 (state == 2'b01) ? 4'b0100 :
112 (state == 2'b10) ? 4'b0010 :
113 4'b0001) );
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114
115 Switches sw(
116 .address(addr),
117 .data(data),
118 .clk(clk),
119 .wr(wr),
120 .rd(rd),
121 .ledout(leds),
6c46357c 122 .switches({switches[7:1],1'b0})
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123 );
124
06ad3a30 125 UART nouart ( /* no u */
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126 .clk(clk),
127 .wr(wr),
128 .rd(rd),
129 .addr(addr),
130 .data(data),
131 .serial(serio)
132 );
9aa931d1 133
eb0f2fe1 134 InternalRAM ram(
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135 .address(addr),
136 .data(data),
137 .clk(clk),
138 .wr(wr),
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139 .rd(rd)
140 );
06ad3a30 141
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142 Timer tmr(
143 .clk(clk),
144 .wr(wr),
145 .rd(rd),
146 .addr(addr),
147 .data(data),
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148 .irq(tmrirq)
149 );
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150
151 Interrupt intr(
152 .clk(clk),
153 .rd(rd),
154 .wr(wr),
155 .addr(addr),
156 .data(data),
157 .vblank(0),
158 .lcdc(0),
159 .tovf(tmrirq),
160 .serial(0),
161 .buttons(0),
162 .master(irq),
163 .jaddr(jaddr));
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164endmodule
165
166module TestBench();
62940da0 167 reg clk = 1;
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168 wire [15:0] addr;
169 wire [7:0] data;
170 wire wr, rd;
171
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172 wire irq, tmrirq;
173 wire [7:0] jaddr;
174
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175 wire [7:0] leds;
176 wire [7:0] switches;
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177
178 always #10 clk <= ~clk;
179 GBZ80Core core(
180 .clk(clk),
181 .busaddress(addr),
182 .busdata(data),
183 .buswr(wr),
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184 .busrd(rd),
185 .irq(irq),
186 .jaddr(jaddr));
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187
188 ROM rom(
189 .clk(clk),
190 .address(addr),
191 .data(data),
192 .wr(wr),
193 .rd(rd));
194
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195 InternalRAM ram(
196 .address(addr),
197 .data(data),
198 .clk(clk),
199 .wr(wr),
200 .rd(rd));
a85b19a7 201
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202 wire serio;
203 UART uart(
204 .addr(addr),
205 .data(data),
206 .clk(clk),
207 .wr(wr),
208 .rd(rd),
209 .serial(serio));
a85b19a7 210
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211 Timer tmr(
212 .clk(clk),
213 .wr(wr),
214 .rd(rd),
215 .addr(addr),
216 .data(data),
217 .irq(tmrirq));
218
219 Interrupt intr(
220 .clk(clk),
221 .rd(rd),
222 .wr(wr),
223 .addr(addr),
224 .data(data),
225 .vblank(0),
226 .lcdc(0),
227 .tovf(tmrirq),
228 .serial(0),
229 .buttons(0),
230 .master(irq),
231 .jaddr(jaddr));
232
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233 Switches sw(
234 .clk(clk),
235 .address(addr),
236 .data(data),
237 .wr(wr),
238 .rd(rd),
239 .switches(switches),
240 .ledout(leds));
a85b19a7 241endmodule
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