Fix the UART, and set it to 19k2 for more stable operation. Make the downloader a...
[fpgaboy.git] / System.v
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a85b19a7
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
a8f4468d 9 reg rdlatch = 0;
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10 reg [7:0] odata;
11
91c74a3f 12 // synthesis attribute ram_style of rom is block
fe3dc890 13 reg [7:0] rom [1023:0];
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14 initial $readmemh("rom.hex", rom);
15
16 wire decode = address[15:13] == 0;
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17 always @(posedge clk) begin
18 rdlatch <= rd && decode;
2854e399 19 odata <= rom[address[10:0]];
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20 end
21 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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22endmodule
23
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24module BootstrapROM(
25 input [15:0] address,
26 inout [7:0] data,
27 input clk,
28 input wr, rd);
29
a8f4468d 30 reg rdlatch = 0;
e29171aa 31 reg [7:0] addrlatch = 0;
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32 reg romno = 0, romnotmp = 0;
33 reg [7:0] brom0 [255:0];
34 reg [7:0] brom1 [255:0];
35
36 initial $readmemh("fpgaboot.hex", brom0);
37 initial $readmemh("gbboot.hex", brom1);
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38
39 wire decode = address[15:8] == 0;
49c326da 40 wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa 41 always @(posedge clk) begin
a8f4468d 42 rdlatch <= rd && decode;
e29171aa 43 addrlatch <= address[7:0];
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44 if (wr && decode) romnotmp <= data[0];
45 if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa 46 end
a8f4468d 47 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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48endmodule
49
50module MiniRAM(
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51 input [15:0] address,
52 inout [7:0] data,
53 input clk,
54 input wr, rd);
55
56 reg [7:0] ram [127:0];
57
58 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d 59 reg rdlatch = 0;
6bd4619b 60 reg [7:0] odata;
a8f4468d 61 assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b 62
68ce013e 63 always @(posedge clk)
6bd4619b 64 begin
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65 rdlatch <= rd && decode;
66 if (decode) // This has to go this way. The only way XST knows how to do
67 begin // block ram is chip select, write enable, and always
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68 if (wr) // reading. "else if rd" does not cut it ...
69 ram[address[6:0]] <= data;
70 odata <= ram[address[6:0]];
71 end
72 end
c279b666 73endmodule
6bd4619b 74
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75module CellularRAM(
76 input clk,
77 input [15:0] address,
78 inout [7:0] data,
79 input wr, rd,
80 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
81 output wire [22:0] cr_A,
82 inout [15:0] cr_DQ);
83
84 parameter ADDR_PROGADDRH = 16'hFF60;
85 parameter ADDR_PROGADDRM = 16'hFF61;
86 parameter ADDR_PROGADDRL = 16'hFF62;
87 parameter ADDR_PROGDATA = 16'hFF63;
88
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89 reg rdlatch = 0, wrlatch = 0;
90 reg [15:0] addrlatch = 0;
91 reg [7:0] datalatch = 0;
92
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93 reg [7:0] progaddrh, progaddrm, progaddrl;
94
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95 reg [22:0] progaddr;
96
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97 assign cr_nADV = 0; /* Addresses are always valid! :D */
98 assign cr_nCE = 0; /* The chip is enabled */
99 assign cr_nLB = 0; /* Lower byte is enabled */
100 assign cr_nUB = 0; /* Upper byte is enabled */
101 assign cr_CRE = 0; /* Data writes, not config */
102 assign cr_CLK = 0; /* Clock? I think not! */
103
a8f4468d 104 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
74610a87 105
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106 assign cr_nOE = decode ? ~rdlatch : 1;
107 assign cr_nWE = decode ? ~wrlatch : 1;
74610a87 108
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109 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
110 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
111 (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
1eefdc8e 112 (addrlatch == ADDR_PROGDATA) ? progaddr :
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113 23'b0;
114
115 reg [7:0] regbuf;
116
a8f4468d 117 always @(posedge clk) begin
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118 case (address)
119 ADDR_PROGADDRH: if (wr) progaddrh <= data;
120 ADDR_PROGADDRM: if (wr) progaddrm <= data;
121 ADDR_PROGADDRL: if (wr) progaddrl <= data;
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122 ADDR_PROGDATA: if (rd || wr) begin
123 progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]};
124 {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1;
125 end
74610a87 126 endcase
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127 rdlatch <= rd;
128 wrlatch <= wr;
129 addrlatch <= address;
130 datalatch <= data;
131 end
74610a87 132
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133 assign data = (rdlatch && decode) ?
134 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
135 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
136 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
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137 cr_DQ
138 : 8'bzzzzzzzz;
139endmodule
140
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141module InternalRAM(
142 input [15:0] address,
143 inout [7:0] data,
144 input clk,
145 input wr, rd);
146
fe3dc890 147 // synthesis attribute ram_style of ram is block
616eebe0 148 reg [7:0] ram [8191:0];
a85b19a7 149
74610a87 150 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7 151 reg [7:0] odata;
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152 reg rdlatch = 0;
153 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 154
68ce013e 155 always @(posedge clk)
a85b19a7 156 begin
a8f4468d 157 rdlatch <= rd && decode;
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158 if (decode) // This has to go this way. The only way XST knows how to do
159 begin // block ram is chip select, write enable, and always
95143d64 160 if (wr) // reading. "else if rd" does not cut it ...
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161 ram[address[12:0]] <= data;
162 odata <= ram[address[12:0]];
c87db60a 163 end
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164 end
165endmodule
166
167module Switches(
168 input [15:0] address,
169 inout [7:0] data,
170 input clk,
171 input wr, rd,
172 input [7:0] switches,
9c834ff2 173 output reg [7:0] ledout = 0);
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174
175 wire decode = address == 16'hFF51;
176 reg [7:0] odata;
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177 reg rdlatch = 0;
178 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 179
68ce013e 180 always @(posedge clk)
a85b19a7 181 begin
a8f4468d 182 rdlatch <= rd && decode;
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183 if (decode && rd)
184 odata <= switches;
185 else if (decode && wr)
186 ledout <= data;
187 end
188endmodule
189
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190`ifdef isim
191module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
192endmodule
193`endif
194
a85b19a7 195module CoreTop(
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196`ifdef isim
197 output reg vgaclk = 0,
198 output reg clk = 0,
199`else
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200 input xtal,
201 input [7:0] switches,
ff7fd7f2 202 input [3:0] buttons,
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203 output wire [7:0] leds,
204 output serio,
298e8085 205 input serin,
a85b19a7 206 output wire [3:0] digits,
00573fd5 207 output wire [7:0] seven,
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208 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
209 output wire [22:0] cr_A,
210 inout [15:0] cr_DQ,
e7fb589a 211`endif
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212 output wire hs, vs,
213 output wire [2:0] r, g,
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214 output wire [1:0] b,
215 output wire soundl, soundr);
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216
217`ifdef isim
218 always #62 clk <= ~clk;
219 always #100 vgaclk <= ~vgaclk;
220
221 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 222
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223 wire [7:0] leds;
224 wire serio;
298e8085 225 wire serin = 1;
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226 wire [3:0] digits;
227 wire [7:0] seven;
228 wire [7:0] switches = 8'b0;
229 wire [3:0] buttons = 4'b0;
230`else
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231 wire xtalb, clk, vgaclk;
232 IBUFG iclkbuf(.O(xtalb), .I(xtal));
233 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
234 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
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235`endif
236
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237 wire [15:0] addr [1:0];
238 wire [7:0] data [1:0];
239 wire wr [1:0], rd [1:0];
f8db6448 240
00573fd5 241 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 242 wire [7:0] jaddr;
6c46357c 243 wire [1:0] state;
179b4347 244
a85b19a7 245 GBZ80Core core(
179b4347 246 .clk(clk),
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247 .bus0address(addr[0]),
248 .bus0data(data[0]),
249 .bus0wr(wr[0]),
250 .bus0rd(rd[0]),
251 .bus1address(addr[1]),
252 .bus1data(data[1]),
253 .bus1wr(wr[1]),
254 .bus1rd(rd[1]),
f8db6448 255 .irq(irq),
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256 .jaddr(jaddr),
257 .state(state));
a85b19a7 258
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259 BootstrapROM brom(
260 .address(addr[1]),
261 .data(data[1]),
262 .clk(clk),
263 .wr(wr[1]),
264 .rd(rd[1]));
265
74610a87 266`ifdef isim
a85b19a7 267 ROM rom(
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268 .address(addr[0]),
269 .data(data[0]),
a85b19a7 270 .clk(clk),
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271 .wr(wr[0]),
272 .rd(rd[0]));
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273`else
274 CellularRAM cellram(
275 .address(addr[0]),
276 .data(data[0]),
277 .clk(clk),
278 .wr(wr[0]),
7c1b9e8e 279 .rd(rd[0]),
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280 .cr_nADV(cr_nADV),
281 .cr_nCE(cr_nCE),
282 .cr_nOE(cr_nOE),
7c1b9e8e 283 .cr_nWE(cr_nWE),
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284 .cr_CRE(cr_CRE),
285 .cr_nLB(cr_nLB),
286 .cr_nUB(cr_nUB),
287 .cr_CLK(cr_CLK),
288 .cr_A(cr_A),
289 .cr_DQ(cr_DQ));
290`endif
a85b19a7 291
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292 wire lcdhs, lcdvs, lcdclk;
293 wire [2:0] lcdr, lcdg;
294 wire [1:0] lcdb;
295
537e1f83 296 LCDC lcdc(
537e1f83 297 .clk(clk),
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298 .addr(addr[0]),
299 .data(data[0]),
300 .wr(wr[0]),
301 .rd(rd[0]),
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302 .lcdcirq(lcdcirq),
303 .vblankirq(vblankirq),
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304 .lcdclk(lcdclk),
305 .lcdhs(lcdhs),
306 .lcdvs(lcdvs),
307 .lcdr(lcdr),
308 .lcdg(lcdg),
309 .lcdb(lcdb));
310
311 Framebuffer fb(
312 .lcdclk(lcdclk),
313 .lcdhs(lcdhs),
314 .lcdvs(lcdvs),
315 .lcdr(lcdr),
316 .lcdg(lcdg),
317 .lcdb(lcdb),
318 .vgaclk(vgaclk),
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319 .vgahs(hs),
320 .vgavs(vs),
321 .vgar(r),
322 .vgag(g),
323 .vgab(b));
537e1f83 324
a85b19a7 325 AddrMon amon(
eb0f2fe1 326 .clk(clk),
91c74a3f 327 .addr(addr[0]),
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328 .digit(digits),
329 .out(seven),
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330 .freeze(buttons[0]),
331 .periods(
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332 (state == 2'b00) ? 4'b0010 :
333 (state == 2'b01) ? 4'b0001 :
334 (state == 2'b10) ? 4'b1000 :
335 4'b0100) );
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336
337 Switches sw(
a85b19a7 338 .clk(clk),
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339 .address(addr[0]),
340 .data(data[0]),
341 .wr(wr[0]),
342 .rd(rd[0]),
a85b19a7 343 .ledout(leds),
fc443a4f 344 .switches(switches)
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345 );
346
06ad3a30 347 UART nouart ( /* no u */
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348 .clk(clk),
349 .addr(addr[0]),
350 .data(data[0]),
351 .wr(wr[0]),
352 .rd(rd[0]),
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353 .serial(serio),
354 .serialrx(serin)
eb0f2fe1 355 );
9aa931d1 356
eb0f2fe1 357 InternalRAM ram(
9aa931d1 358 .clk(clk),
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359 .address(addr[0]),
360 .data(data[0]),
361 .wr(wr[0]),
362 .rd(rd[0])
eb0f2fe1 363 );
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364
365 MiniRAM mram(
6bd4619b 366 .clk(clk),
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367 .address(addr[1]),
368 .data(data[1]),
369 .wr(wr[1]),
370 .rd(rd[1])
6bd4619b 371 );
06ad3a30 372
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373 Timer tmr(
374 .clk(clk),
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375 .addr(addr[0]),
376 .data(data[0]),
377 .wr(wr[0]),
378 .rd(rd[0]),
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379 .irq(tmrirq)
380 );
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381
382 Interrupt intr(
383 .clk(clk),
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384 .addr(addr[0]),
385 .data(data[0]),
386 .wr(wr[0]),
387 .rd(rd[0]),
00573fd5 388 .vblank(vblankirq),
537e1f83 389 .lcdc(lcdcirq),
06ad3a30 390 .tovf(tmrirq),
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391 .serial(1'b0),
392 .buttons(1'b0),
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393 .master(irq),
394 .jaddr(jaddr));
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395
396 Soundcore sound(
397 .core_clk(clk),
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398 .addr(addr[0]),
399 .data(data[0]),
400 .rd(rd[0]),
401 .wr(wr[0]),
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402 .snd_data_l(soundl),
403 .snd_data_r(soundr));
a85b19a7 404endmodule
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