Some LCDC IRQ stuffs. Working on fixing ldm_a
[fpgaboy.git] / System.v
CommitLineData
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
a85b19a7 28 reg [7:0] odata;
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29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
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33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
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36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
c87db60a 38 end
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39 end
40endmodule
41
42module Switches(
43 input [15:0] address,
44 inout [7:0] data,
45 input clk,
46 input wr, rd,
47 input [7:0] switches,
9c834ff2 48 output reg [7:0] ledout = 0);
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49
50 wire decode = address == 16'hFF51;
51 reg [7:0] odata;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
56 if (decode && rd)
57 odata <= switches;
58 else if (decode && wr)
59 ledout <= data;
60 end
61endmodule
62
63module CoreTop(
64 input xtal,
65 input [7:0] switches,
ff7fd7f2 66 input [3:0] buttons,
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67 output wire [7:0] leds,
68 output serio,
69 output wire [3:0] digits,
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70 output wire [7:0] seven,
71 output wire hs, vs,
72 output wire [2:0] r, g,
73 output wire [1:0] b);
a85b19a7 74
06ad3a30 75 wire clk;
a85b19a7 76 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
6c46357c 77
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78 wire [15:0] addr;
79 wire [7:0] data;
80 wire wr, rd;
f8db6448 81
00573fd5 82 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 83 wire [7:0] jaddr;
6c46357c 84 wire [1:0] state;
179b4347 85
a85b19a7 86 GBZ80Core core(
179b4347 87 .clk(clk),
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88 .busaddress(addr),
89 .busdata(data),
90 .buswr(wr),
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91 .busrd(rd),
92 .irq(irq),
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93 .jaddr(jaddr),
94 .state(state));
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95
96 ROM rom(
97 .address(addr),
98 .data(data),
99 .clk(clk),
100 .wr(wr),
101 .rd(rd));
102
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103 LCDC lcdc(
104 .addr(addr),
105 .data(data),
106 .clk(clk),
107 .wr(wr),
108 .rd(rd),
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109 .lcdcirq(lcdcirq),
110 .vblankirq(vblankirq),
111 .vgahs(hs),
112 .vgavs(vs),
113 .vgar(r),
114 .vgag(g),
115 .vgab(b));
537e1f83 116
a85b19a7 117 AddrMon amon(
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118 .addr(addr),
119 .clk(clk),
120 .digit(digits),
121 .out(seven),
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122 .freeze(buttons[0]),
123 .periods(
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124 (state == 2'b00) ? 4'b0010 :
125 (state == 2'b01) ? 4'b0001 :
126 (state == 2'b10) ? 4'b1000 :
127 4'b0100) );
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128
129 Switches sw(
130 .address(addr),
131 .data(data),
132 .clk(clk),
133 .wr(wr),
134 .rd(rd),
135 .ledout(leds),
fc443a4f 136 .switches(switches)
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137 );
138
06ad3a30 139 UART nouart ( /* no u */
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140 .clk(clk),
141 .wr(wr),
142 .rd(rd),
143 .addr(addr),
144 .data(data),
145 .serial(serio)
146 );
9aa931d1 147
eb0f2fe1 148 InternalRAM ram(
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149 .address(addr),
150 .data(data),
151 .clk(clk),
152 .wr(wr),
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153 .rd(rd)
154 );
06ad3a30 155
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156 Timer tmr(
157 .clk(clk),
158 .wr(wr),
159 .rd(rd),
160 .addr(addr),
161 .data(data),
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162 .irq(tmrirq)
163 );
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164
165 Interrupt intr(
166 .clk(clk),
167 .rd(rd),
168 .wr(wr),
169 .addr(addr),
170 .data(data),
00573fd5 171 .vblank(vblankirq),
537e1f83 172 .lcdc(lcdcirq),
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173 .tovf(tmrirq),
174 .serial(0),
175 .buttons(0),
176 .master(irq),
177 .jaddr(jaddr));
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178endmodule
179
180module TestBench();
62940da0 181 reg clk = 1;
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182 wire [15:0] addr;
183 wire [7:0] data;
184 wire wr, rd;
185
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186 wire irq, tmrirq;
187 wire [7:0] jaddr;
188
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189 wire [7:0] leds;
190 wire [7:0] switches;
a85b19a7 191
179b4347 192 always #62 clk <= ~clk;
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193 GBZ80Core core(
194 .clk(clk),
195 .busaddress(addr),
196 .busdata(data),
197 .buswr(wr),
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198 .busrd(rd),
199 .irq(irq),
200 .jaddr(jaddr));
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201
202 ROM rom(
203 .clk(clk),
204 .address(addr),
205 .data(data),
206 .wr(wr),
207 .rd(rd));
208
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209 InternalRAM ram(
210 .address(addr),
211 .data(data),
212 .clk(clk),
213 .wr(wr),
214 .rd(rd));
a85b19a7 215
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216 wire serio;
217 UART uart(
218 .addr(addr),
219 .data(data),
220 .clk(clk),
221 .wr(wr),
222 .rd(rd),
223 .serial(serio));
a85b19a7 224
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225 Timer tmr(
226 .clk(clk),
227 .wr(wr),
228 .rd(rd),
229 .addr(addr),
230 .data(data),
231 .irq(tmrirq));
232
233 Interrupt intr(
234 .clk(clk),
235 .rd(rd),
236 .wr(wr),
237 .addr(addr),
238 .data(data),
239 .vblank(0),
240 .lcdc(0),
241 .tovf(tmrirq),
242 .serial(0),
243 .buttons(0),
244 .master(irq),
245 .jaddr(jaddr));
246
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247 Switches sw(
248 .clk(clk),
249 .address(addr),
250 .data(data),
251 .wr(wr),
252 .rd(rd),
253 .switches(switches),
254 .ledout(leds));
a85b19a7 255endmodule
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