New generation makefile. Code that will reliably break the machine.
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
a85b19a7 28 reg [7:0] odata;
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29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
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33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
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36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
c87db60a 38 end
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39 end
40endmodule
41
42module Switches(
43 input [15:0] address,
44 inout [7:0] data,
45 input clk,
46 input wr, rd,
47 input [7:0] switches,
9c834ff2 48 output reg [7:0] ledout = 0);
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49
50 wire decode = address == 16'hFF51;
51 reg [7:0] odata;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
56 if (decode && rd)
57 odata <= switches;
58 else if (decode && wr)
59 ledout <= data;
60 end
61endmodule
62
63module CoreTop(
64 input xtal,
65 input [7:0] switches,
ff7fd7f2 66 input [3:0] buttons,
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67 output wire [7:0] leds,
68 output serio,
69 output wire [3:0] digits,
70 output wire [7:0] seven);
71
06ad3a30 72 wire clk;
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73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
74
75 wire [15:0] addr;
76 wire [7:0] data;
77 wire wr, rd;
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78
79 wire irq, tmrirq;
80 wire [7:0] jaddr;
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81
82 GBZ80Core core(
83 .clk(clk),
84 .busaddress(addr),
85 .busdata(data),
86 .buswr(wr),
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87 .busrd(rd),
88 .irq(irq),
89 .jaddr(jaddr));
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90
91 ROM rom(
92 .address(addr),
93 .data(data),
94 .clk(clk),
95 .wr(wr),
96 .rd(rd));
97
98 AddrMon amon(
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99 .addr(addr),
100 .clk(clk),
101 .digit(digits),
102 .out(seven),
103 .freeze(buttons[0]));
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104
105 Switches sw(
106 .address(addr),
107 .data(data),
108 .clk(clk),
109 .wr(wr),
110 .rd(rd),
111 .ledout(leds),
112 .switches(switches)
113 );
114
06ad3a30 115 UART nouart ( /* no u */
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116 .clk(clk),
117 .wr(wr),
118 .rd(rd),
119 .addr(addr),
120 .data(data),
121 .serial(serio)
122 );
9aa931d1 123
eb0f2fe1 124 InternalRAM ram(
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125 .address(addr),
126 .data(data),
127 .clk(clk),
128 .wr(wr),
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129 .rd(rd)
130 );
06ad3a30 131
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132 Timer tmr(
133 .clk(clk),
134 .wr(wr),
135 .rd(rd),
136 .addr(addr),
137 .data(data),
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138 .irq(tmrirq)
139 );
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140
141 Interrupt intr(
142 .clk(clk),
143 .rd(rd),
144 .wr(wr),
145 .addr(addr),
146 .data(data),
147 .vblank(0),
148 .lcdc(0),
149 .tovf(tmrirq),
150 .serial(0),
151 .buttons(0),
152 .master(irq),
153 .jaddr(jaddr));
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154endmodule
155
156module TestBench();
62940da0 157 reg clk = 1;
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158 wire [15:0] addr;
159 wire [7:0] data;
160 wire wr, rd;
161
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162 wire irq, tmrirq;
163 wire [7:0] jaddr;
164
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165 wire [7:0] leds;
166 wire [7:0] switches;
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167
168 always #10 clk <= ~clk;
169 GBZ80Core core(
170 .clk(clk),
171 .busaddress(addr),
172 .busdata(data),
173 .buswr(wr),
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174 .busrd(rd),
175 .irq(irq),
176 .jaddr(jaddr));
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177
178 ROM rom(
179 .clk(clk),
180 .address(addr),
181 .data(data),
182 .wr(wr),
183 .rd(rd));
184
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185 InternalRAM ram(
186 .address(addr),
187 .data(data),
188 .clk(clk),
189 .wr(wr),
190 .rd(rd));
a85b19a7 191
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192 wire serio;
193 UART uart(
194 .addr(addr),
195 .data(data),
196 .clk(clk),
197 .wr(wr),
198 .rd(rd),
199 .serial(serio));
a85b19a7 200
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201 Timer tmr(
202 .clk(clk),
203 .wr(wr),
204 .rd(rd),
205 .addr(addr),
206 .data(data),
207 .irq(tmrirq));
208
209 Interrupt intr(
210 .clk(clk),
211 .rd(rd),
212 .wr(wr),
213 .addr(addr),
214 .data(data),
215 .vblank(0),
216 .lcdc(0),
217 .tovf(tmrirq),
218 .serial(0),
219 .buttons(0),
220 .master(irq),
221 .jaddr(jaddr));
222
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223 Switches sw(
224 .clk(clk),
225 .address(addr),
226 .data(data),
227 .wr(wr),
228 .rd(rd),
229 .switches(switches),
230 .ledout(leds));
a85b19a7 231endmodule
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