[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] odata;

	// synthesis attribute ram_style of rom is block
	reg [7:0] rom [1023:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		odata <= rom[address[10:0]];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] addrlatch = 0;
	reg [7:0] brom [255:0];
	initial $readmemh("bootstrap.hex", brom);

	wire decode = address[15:8] == 0;
	wire [7:0] odata = brom[addrlatch];
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		addrlatch <= address[7:0];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg rdlatch = 0;
	reg [7:0] odata;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	
	reg rdlatch = 0, wrlatch = 0;
	reg [15:0] addrlatch = 0;
	reg [7:0] datalatch = 0;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = 0;	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
	
	assign cr_nOE = decode ? ~rdlatch : 1;
	assign cr_nWE = decode ? ~wrlatch : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
			(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
			(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
			23'b0;
	
	reg [7:0] regbuf;
	
	always @(posedge clk) begin
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		endcase
		rdlatch <= rd;
		wrlatch <= wr;
		addrlatch <= address;
		datalatch <= data;
	end
	
	assign data = (rdlatch && decode) ?
				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	ROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0])
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWR(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));
	
	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule
Commit	Line	Data
a85b19a7 JW	1
	2	`timescale 1ns / 1ps
	3	module ROM(
	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
a8f4468d	9	reg rdlatch = 0;
2854e399 JW	10	reg [7:0] odata;
2854e399 JW	11
91c74a3f	12	// synthesis attribute ram_style of rom is block
fe3dc890	13	reg [7:0] rom [1023:0];
a85b19a7 JW	14	initial $readmemh("rom.hex", rom);
	15
	16	wire decode = address[15:13] == 0;
a8f4468d JW	17	always @(posedge clk) begin
a8f4468d JW	18	rdlatch <= rd && decode;
2854e399	19	odata <= rom[address[10:0]];
a8f4468d JW	20	end
a8f4468d JW	21	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 JW	22	endmodule
a85b19a7 JW	23
91c74a3f JW	24	module BootstrapROM(
	25	input [15:0] address,
	26	inout [7:0] data,
	27	input clk,
	28	input wr, rd);
	29
a8f4468d	30	reg rdlatch = 0;
e29171aa	31	reg [7:0] addrlatch = 0;
2854e399 JW	32	reg [7:0] brom [255:0];
2854e399 JW	33	initial $readmemh("bootstrap.hex", brom);
91c74a3f JW	34
91c74a3f JW	35	wire decode = address[15:8] == 0;
e29171aa JW	36	wire [7:0] odata = brom[addrlatch];
e29171aa JW	37	always @(posedge clk) begin
a8f4468d	38	rdlatch <= rd && decode;
e29171aa JW	39	addrlatch <= address[7:0];
e29171aa JW	40	end
a8f4468d	41	assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f JW	42	endmodule
	43
	44	module MiniRAM(
6bd4619b JW	45	input [15:0] address,
	46	inout [7:0] data,
	47	input clk,
	48	input wr, rd);
	49
	50	reg [7:0] ram [127:0];
	51
	52	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d	53	reg rdlatch = 0;
6bd4619b	54	reg [7:0] odata;
a8f4468d	55	assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b	56
68ce013e	57	always @(posedge clk)
6bd4619b	58	begin
a8f4468d JW	59	rdlatch <= rd && decode;
	60	if (decode) // This has to go this way. The only way XST knows how to do
	61	begin // block ram is chip select, write enable, and always
6bd4619b JW	62	if (wr) // reading. "else if rd" does not cut it ...
	63	ram[address[6:0]] <= data;
	64	odata <= ram[address[6:0]];
	65	end
	66	end
c279b666	67	endmodule
6bd4619b	68
74610a87 JW	69	module CellularRAM(
	70	input clk,
	71	input [15:0] address,
	72	inout [7:0] data,
	73	input wr, rd,
	74	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	75	output wire [22:0] cr_A,
	76	inout [15:0] cr_DQ);
	77
	78	parameter ADDR_PROGADDRH = 16'hFF60;
	79	parameter ADDR_PROGADDRM = 16'hFF61;
	80	parameter ADDR_PROGADDRL = 16'hFF62;
	81	parameter ADDR_PROGDATA = 16'hFF63;
	82
a8f4468d JW	83	reg rdlatch = 0, wrlatch = 0;
	84	reg [15:0] addrlatch = 0;
	85	reg [7:0] datalatch = 0;
	86
74610a87 JW	87	reg [7:0] progaddrh, progaddrm, progaddrl;
	88
	89	assign cr_nADV = 0; /* Addresses are always valid! :D */
	90	assign cr_nCE = 0; /* The chip is enabled */
	91	assign cr_nLB = 0; /* Lower byte is enabled */
	92	assign cr_nUB = 0; /* Upper byte is enabled */
	93	assign cr_CRE = 0; /* Data writes, not config */
	94	assign cr_CLK = 0; /* Clock? I think not! */
	95
a8f4468d	96	wire decode = (addrlatch[15:14] == 2'b00) /* extrom / \|\| (addrlatch[15:13] == 3'b101) / extram */ \|\| (addrlatch == ADDR_PROGDATA);
74610a87	97
a8f4468d JW	98	assign cr_nOE = decode ? ~rdlatch : 1;
a8f4468d JW	99	assign cr_nWE = decode ? ~wrlatch : 1;
74610a87	100
a8f4468d JW	101	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	102	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
	103	(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
	104	(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
74610a87 JW	105	23'b0;
	106
	107	reg [7:0] regbuf;
	108
a8f4468d	109	always @(posedge clk) begin
74610a87 JW	110	case (address)
	111	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	112	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	113	ADDR_PROGADDRL: if (wr) progaddrl <= data;
	114	endcase
a8f4468d JW	115	rdlatch <= rd;
	116	wrlatch <= wr;
	117	addrlatch <= address;
	118	datalatch <= data;
	119	end
74610a87	120
a8f4468d JW	121	assign data = (rdlatch && decode) ?
	122	(addrlatch == ADDR_PROGADDRH) ? progaddrh :
	123	(addrlatch == ADDR_PROGADDRM) ? progaddrm :
	124	(addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87 JW	125	cr_DQ
	126	: 8'bzzzzzzzz;
	127	endmodule
	128
a85b19a7 JW	129	module InternalRAM(
	130	input [15:0] address,
	131	inout [7:0] data,
	132	input clk,
	133	input wr, rd);
	134
fe3dc890	135	// synthesis attribute ram_style of ram is block
616eebe0	136	reg [7:0] ram [8191:0];
a85b19a7	137
74610a87	138	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	139	reg [7:0] odata;
a8f4468d JW	140	reg rdlatch = 0;
a8f4468d JW	141	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	142
68ce013e	143	always @(posedge clk)
a85b19a7	144	begin
a8f4468d	145	rdlatch <= rd && decode;
74610a87 JW	146	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	147	begin // block ram is chip select, write enable, and always
95143d64	148	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	149	ram[address[12:0]] <= data;
616eebe0 JW	150	odata <= ram[address[12:0]];
c87db60a	151	end
a85b19a7 JW	152	end
	153	endmodule
	154
	155	module Switches(
	156	input [15:0] address,
	157	inout [7:0] data,
	158	input clk,
	159	input wr, rd,
	160	input [7:0] switches,
9c834ff2	161	output reg [7:0] ledout = 0);
a85b19a7 JW	162
	163	wire decode = address == 16'hFF51;
	164	reg [7:0] odata;
a8f4468d JW	165	reg rdlatch = 0;
a8f4468d JW	166	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	167
68ce013e	168	always @(posedge clk)
a85b19a7	169	begin
a8f4468d	170	rdlatch <= rd && decode;
a85b19a7 JW	171	if (decode && rd)
	172	odata <= switches;
	173	else if (decode && wr)
	174	ledout <= data;
	175	end
	176	endmodule
	177
e7fb589a JW	178	`ifdef isim
	179	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	180	endmodule
	181	`endif
	182
a85b19a7	183	module CoreTop(
e7fb589a JW	184	`ifdef isim
	185	output reg vgaclk = 0,
	186	output reg clk = 0,
	187	`else
a85b19a7 JW	188	input xtal,
a85b19a7 JW	189	input [7:0] switches,
ff7fd7f2	190	input [3:0] buttons,
a85b19a7 JW	191	output wire [7:0] leds,
	192	output serio,
	193	output wire [3:0] digits,
00573fd5	194	output wire [7:0] seven,
74610a87 JW	195	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	196	output wire [22:0] cr_A,
	197	inout [15:0] cr_DQ,
e7fb589a	198	`endif
00573fd5 JW	199	output wire hs, vs,
00573fd5 JW	200	output wire [2:0] r, g,
09c1936c JW	201	output wire [1:0] b,
09c1936c JW	202	output wire soundl, soundr);
e7fb589a JW	203
	204	`ifdef isim
	205	always #62 clk <= ~clk;
	206	always #100 vgaclk <= ~vgaclk;
	207
	208	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	209
e7fb589a JW	210	wire [7:0] leds;
	211	wire serio;
	212	wire [3:0] digits;
	213	wire [7:0] seven;
	214	wire [7:0] switches = 8'b0;
	215	wire [3:0] buttons = 4'b0;
	216	`else
fe3dc890 JW	217	wire xtalb, clk, vgaclk;
	218	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	219	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	220	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	221	`endif
e7fb589a JW	222
91c74a3f JW	223	wire [15:0] addr [1:0];
	224	wire [7:0] data [1:0];
	225	wire wr [1:0], rd [1:0];
f8db6448	226
00573fd5	227	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	228	wire [7:0] jaddr;
6c46357c	229	wire [1:0] state;
179b4347	230
a85b19a7	231	GBZ80Core core(
179b4347	232	.clk(clk),
91c74a3f JW	233	.bus0address(addr[0]),
	234	.bus0data(data[0]),
	235	.bus0wr(wr[0]),
	236	.bus0rd(rd[0]),
	237	.bus1address(addr[1]),
	238	.bus1data(data[1]),
	239	.bus1wr(wr[1]),
	240	.bus1rd(rd[1]),
f8db6448	241	.irq(irq),
6c46357c JW	242	.jaddr(jaddr),
6c46357c JW	243	.state(state));
a85b19a7	244
91c74a3f JW	245	BootstrapROM brom(
	246	.address(addr[1]),
	247	.data(data[1]),
	248	.clk(clk),
	249	.wr(wr[1]),
	250	.rd(rd[1]));
	251
74610a87	252	`ifdef isim
a85b19a7	253	ROM rom(
91c74a3f JW	254	.address(addr[0]),
91c74a3f JW	255	.data(data[0]),
a85b19a7	256	.clk(clk),
91c74a3f JW	257	.wr(wr[0]),
91c74a3f JW	258	.rd(rd[0]));
74610a87 JW	259	`else
	260	CellularRAM cellram(
	261	.address(addr[0]),
	262	.data(data[0]),
	263	.clk(clk),
	264	.wr(wr[0]),
	265	.rd(rd[0])
	266	.cr_nADV(cr_nADV),
	267	.cr_nCE(cr_nCE),
	268	.cr_nOE(cr_nOE),
	269	.cr_nWR(cr_nWE),
	270	.cr_CRE(cr_CRE),
	271	.cr_nLB(cr_nLB),
	272	.cr_nUB(cr_nUB),
	273	.cr_CLK(cr_CLK),
	274	.cr_A(cr_A),
	275	.cr_DQ(cr_DQ));
	276	`endif
a85b19a7	277
fe3dc890 JW	278	wire lcdhs, lcdvs, lcdclk;
	279	wire [2:0] lcdr, lcdg;
	280	wire [1:0] lcdb;
	281
537e1f83	282	LCDC lcdc(
537e1f83	283	.clk(clk),
91c74a3f JW	284	.addr(addr[0]),
	285	.data(data[0]),
	286	.wr(wr[0]),
	287	.rd(rd[0]),
00573fd5 JW	288	.lcdcirq(lcdcirq),
00573fd5 JW	289	.vblankirq(vblankirq),
fe3dc890 JW	290	.lcdclk(lcdclk),
	291	.lcdhs(lcdhs),
	292	.lcdvs(lcdvs),
	293	.lcdr(lcdr),
	294	.lcdg(lcdg),
	295	.lcdb(lcdb));
	296
	297	Framebuffer fb(
	298	.lcdclk(lcdclk),
	299	.lcdhs(lcdhs),
	300	.lcdvs(lcdvs),
	301	.lcdr(lcdr),
	302	.lcdg(lcdg),
	303	.lcdb(lcdb),
	304	.vgaclk(vgaclk),
00573fd5 JW	305	.vgahs(hs),
	306	.vgavs(vs),
	307	.vgar(r),
	308	.vgag(g),
	309	.vgab(b));
537e1f83	310
a85b19a7	311	AddrMon amon(
eb0f2fe1	312	.clk(clk),
91c74a3f	313	.addr(addr[0]),
eb0f2fe1 JW	314	.digit(digits),
eb0f2fe1 JW	315	.out(seven),
6c46357c JW	316	.freeze(buttons[0]),
6c46357c JW	317	.periods(
179b4347 JW	318	(state == 2'b00) ? 4'b0010 :
	319	(state == 2'b01) ? 4'b0001 :
	320	(state == 2'b10) ? 4'b1000 :
	321	4'b0100) );
a85b19a7 JW	322
a85b19a7 JW	323	Switches sw(
a85b19a7	324	.clk(clk),
91c74a3f JW	325	.address(addr[0]),
	326	.data(data[0]),
	327	.wr(wr[0]),
	328	.rd(rd[0]),
a85b19a7	329	.ledout(leds),
fc443a4f	330	.switches(switches)
a85b19a7 JW	331	);
a85b19a7 JW	332
06ad3a30	333	UART nouart ( /* no u */
91c74a3f JW	334	.clk(clk),
	335	.addr(addr[0]),
	336	.data(data[0]),
	337	.wr(wr[0]),
	338	.rd(rd[0]),
eb0f2fe1 JW	339	.serial(serio)
eb0f2fe1 JW	340	);
9aa931d1	341
eb0f2fe1	342	InternalRAM ram(
9aa931d1	343	.clk(clk),
91c74a3f JW	344	.address(addr[0]),
	345	.data(data[0]),
	346	.wr(wr[0]),
	347	.rd(rd[0])
eb0f2fe1	348	);
6bd4619b JW	349
6bd4619b JW	350	MiniRAM mram(
6bd4619b	351	.clk(clk),
91c74a3f JW	352	.address(addr[1]),
	353	.data(data[1]),
	354	.wr(wr[1]),
	355	.rd(rd[1])
6bd4619b	356	);
06ad3a30	357
06ad3a30 JW	358	Timer tmr(
06ad3a30 JW	359	.clk(clk),
91c74a3f JW	360	.addr(addr[0]),
	361	.data(data[0]),
	362	.wr(wr[0]),
	363	.rd(rd[0]),
eb0f2fe1 JW	364	.irq(tmrirq)
eb0f2fe1 JW	365	);
06ad3a30 JW	366
	367	Interrupt intr(
	368	.clk(clk),
91c74a3f JW	369	.addr(addr[0]),
	370	.data(data[0]),
	371	.wr(wr[0]),
	372	.rd(rd[0]),
00573fd5	373	.vblank(vblankirq),
537e1f83	374	.lcdc(lcdcirq),
06ad3a30	375	.tovf(tmrirq),
e7fb589a JW	376	.serial(1'b0),
e7fb589a JW	377	.buttons(1'b0),
06ad3a30 JW	378	.master(irq),
06ad3a30 JW	379	.jaddr(jaddr));
09c1936c JW	380
	381	Soundcore sound(
	382	.core_clk(clk),
91c74a3f JW	383	.addr(addr[0]),
	384	.data(data[0]),
	385	.rd(rd[0]),
	386	.wr(wr[0]),
09c1936c JW	387	.snd_data_l(soundl),
09c1936c JW	388	.snd_data_r(soundr));
a85b19a7	389	endmodule