Add mock up LCDC
[fpgaboy.git] / System.v
CommitLineData
a85b19a7
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
a85b19a7 28 reg [7:0] odata;
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29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
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33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
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36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
c87db60a 38 end
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39 end
40endmodule
41
42module Switches(
43 input [15:0] address,
44 inout [7:0] data,
45 input clk,
46 input wr, rd,
47 input [7:0] switches,
9c834ff2 48 output reg [7:0] ledout = 0);
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49
50 wire decode = address == 16'hFF51;
51 reg [7:0] odata;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
56 if (decode && rd)
57 odata <= switches;
58 else if (decode && wr)
59 ledout <= data;
60 end
61endmodule
62
63module CoreTop(
64 input xtal,
65 input [7:0] switches,
ff7fd7f2 66 input [3:0] buttons,
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67 output wire [7:0] leds,
68 output serio,
69 output wire [3:0] digits,
70 output wire [7:0] seven);
71
06ad3a30 72 wire clk;
a85b19a7 73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
6c46357c 74
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75 wire [15:0] addr;
76 wire [7:0] data;
77 wire wr, rd;
f8db6448 78
537e1f83 79 wire irq, tmrirq, lcdcirq;
f8db6448 80 wire [7:0] jaddr;
6c46357c 81 wire [1:0] state;
179b4347 82
a85b19a7 83 GBZ80Core core(
179b4347 84 .clk(clk),
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85 .busaddress(addr),
86 .busdata(data),
87 .buswr(wr),
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88 .busrd(rd),
89 .irq(irq),
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90 .jaddr(jaddr),
91 .state(state));
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92
93 ROM rom(
94 .address(addr),
95 .data(data),
96 .clk(clk),
97 .wr(wr),
98 .rd(rd));
99
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100 LCDC lcdc(
101 .addr(addr),
102 .data(data),
103 .clk(clk),
104 .wr(wr),
105 .rd(rd),
106 .irq(lcdcirq));
107
a85b19a7 108 AddrMon amon(
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109 .addr(addr),
110 .clk(clk),
111 .digit(digits),
112 .out(seven),
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113 .freeze(buttons[0]),
114 .periods(
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115 (state == 2'b00) ? 4'b0010 :
116 (state == 2'b01) ? 4'b0001 :
117 (state == 2'b10) ? 4'b1000 :
118 4'b0100) );
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119
120 Switches sw(
121 .address(addr),
122 .data(data),
123 .clk(clk),
124 .wr(wr),
125 .rd(rd),
126 .ledout(leds),
fc443a4f 127 .switches(switches)
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128 );
129
06ad3a30 130 UART nouart ( /* no u */
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131 .clk(clk),
132 .wr(wr),
133 .rd(rd),
134 .addr(addr),
135 .data(data),
136 .serial(serio)
137 );
9aa931d1 138
eb0f2fe1 139 InternalRAM ram(
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140 .address(addr),
141 .data(data),
142 .clk(clk),
143 .wr(wr),
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144 .rd(rd)
145 );
06ad3a30 146
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147 Timer tmr(
148 .clk(clk),
149 .wr(wr),
150 .rd(rd),
151 .addr(addr),
152 .data(data),
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153 .irq(tmrirq)
154 );
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155
156 Interrupt intr(
157 .clk(clk),
158 .rd(rd),
159 .wr(wr),
160 .addr(addr),
161 .data(data),
162 .vblank(0),
537e1f83 163 .lcdc(lcdcirq),
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164 .tovf(tmrirq),
165 .serial(0),
166 .buttons(0),
167 .master(irq),
168 .jaddr(jaddr));
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169endmodule
170
171module TestBench();
62940da0 172 reg clk = 1;
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173 wire [15:0] addr;
174 wire [7:0] data;
175 wire wr, rd;
176
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177 wire irq, tmrirq;
178 wire [7:0] jaddr;
179
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180 wire [7:0] leds;
181 wire [7:0] switches;
a85b19a7 182
179b4347 183 always #62 clk <= ~clk;
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184 GBZ80Core core(
185 .clk(clk),
186 .busaddress(addr),
187 .busdata(data),
188 .buswr(wr),
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189 .busrd(rd),
190 .irq(irq),
191 .jaddr(jaddr));
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192
193 ROM rom(
194 .clk(clk),
195 .address(addr),
196 .data(data),
197 .wr(wr),
198 .rd(rd));
199
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200 InternalRAM ram(
201 .address(addr),
202 .data(data),
203 .clk(clk),
204 .wr(wr),
205 .rd(rd));
a85b19a7 206
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207 wire serio;
208 UART uart(
209 .addr(addr),
210 .data(data),
211 .clk(clk),
212 .wr(wr),
213 .rd(rd),
214 .serial(serio));
a85b19a7 215
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216 Timer tmr(
217 .clk(clk),
218 .wr(wr),
219 .rd(rd),
220 .addr(addr),
221 .data(data),
222 .irq(tmrirq));
223
224 Interrupt intr(
225 .clk(clk),
226 .rd(rd),
227 .wr(wr),
228 .addr(addr),
229 .data(data),
230 .vblank(0),
231 .lcdc(0),
232 .tovf(tmrirq),
233 .serial(0),
234 .buttons(0),
235 .master(irq),
236 .jaddr(jaddr));
237
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238 Switches sw(
239 .clk(clk),
240 .address(addr),
241 .data(data),
242 .wr(wr),
243 .rd(rd),
244 .switches(switches),
245 .ledout(leds));
a85b19a7 246endmodule
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