Flop the clock polarity of the LCDC around.
[fpgaboy.git] / System.v
CommitLineData
a85b19a7
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
91c74a3f 9 // synthesis attribute ram_style of rom is block
fe3dc890 10 reg [7:0] rom [1023:0];
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11 initial $readmemh("rom.hex", rom);
12
13 wire decode = address[15:13] == 0;
fe3dc890 14 wire [7:0] odata = rom[address[10:0]];
a85b19a7 15 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
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16endmodule
17
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18module BootstrapROM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] rom [255:0];
25 initial $readmemh("bootstrap.hex", rom);
26
27 wire decode = address[15:8] == 0;
28 wire [7:0] odata = rom[address[7:0]];
29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30endmodule
31
32module MiniRAM(
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33 input [15:0] address,
34 inout [7:0] data,
35 input clk,
36 input wr, rd);
37
38 reg [7:0] ram [127:0];
39
40 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
41 reg [7:0] odata;
42 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
43
68ce013e 44 always @(posedge clk)
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45 begin
46 if (decode) // This has to go this way. The only way XST knows how to do
47 begin // block ram is chip select, write enable, and always
48 if (wr) // reading. "else if rd" does not cut it ...
49 ram[address[6:0]] <= data;
50 odata <= ram[address[6:0]];
51 end
52 end
c279b666 53endmodule
6bd4619b 54
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55module InternalRAM(
56 input [15:0] address,
57 inout [7:0] data,
58 input clk,
59 input wr, rd);
60
fe3dc890 61 // synthesis attribute ram_style of ram is block
616eebe0 62 reg [7:0] ram [8191:0];
a85b19a7 63
c87db60a 64 wire decode = address[15:13] == 3'b110;
a85b19a7 65 reg [7:0] odata;
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66 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
67
68ce013e 68 always @(posedge clk)
a85b19a7 69 begin
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70 if (decode) // This has to go this way. The only way XST knows how to do
71 begin // block ram is chip select, write enable, and always
72 if (wr) // reading. "else if rd" does not cut it ...
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73 ram[address[12:0]] <= data;
74 odata <= ram[address[12:0]];
c87db60a 75 end
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76 end
77endmodule
78
79module Switches(
80 input [15:0] address,
81 inout [7:0] data,
82 input clk,
83 input wr, rd,
84 input [7:0] switches,
9c834ff2 85 output reg [7:0] ledout = 0);
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86
87 wire decode = address == 16'hFF51;
88 reg [7:0] odata;
89 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
90
68ce013e 91 always @(posedge clk)
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92 begin
93 if (decode && rd)
94 odata <= switches;
95 else if (decode && wr)
96 ledout <= data;
97 end
98endmodule
99
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100`ifdef isim
101module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
102endmodule
103`endif
104
a85b19a7 105module CoreTop(
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106`ifdef isim
107 output reg vgaclk = 0,
108 output reg clk = 0,
109`else
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110 input xtal,
111 input [7:0] switches,
ff7fd7f2 112 input [3:0] buttons,
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113 output wire [7:0] leds,
114 output serio,
115 output wire [3:0] digits,
00573fd5 116 output wire [7:0] seven,
e7fb589a 117`endif
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118 output wire hs, vs,
119 output wire [2:0] r, g,
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120 output wire [1:0] b,
121 output wire soundl, soundr);
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122
123`ifdef isim
124 always #62 clk <= ~clk;
125 always #100 vgaclk <= ~vgaclk;
126
127 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 128
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129 wire [7:0] leds;
130 wire serio;
131 wire [3:0] digits;
132 wire [7:0] seven;
133 wire [7:0] switches = 8'b0;
134 wire [3:0] buttons = 4'b0;
135`else
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136 wire xtalb, clk, vgaclk;
137 IBUFG iclkbuf(.O(xtalb), .I(xtal));
138 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
139 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
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140`endif
141
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142 wire [15:0] addr [1:0];
143 wire [7:0] data [1:0];
144 wire wr [1:0], rd [1:0];
f8db6448 145
00573fd5 146 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 147 wire [7:0] jaddr;
6c46357c 148 wire [1:0] state;
179b4347 149
a85b19a7 150 GBZ80Core core(
179b4347 151 .clk(clk),
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152 .bus0address(addr[0]),
153 .bus0data(data[0]),
154 .bus0wr(wr[0]),
155 .bus0rd(rd[0]),
156 .bus1address(addr[1]),
157 .bus1data(data[1]),
158 .bus1wr(wr[1]),
159 .bus1rd(rd[1]),
f8db6448 160 .irq(irq),
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161 .jaddr(jaddr),
162 .state(state));
a85b19a7 163
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164 BootstrapROM brom(
165 .address(addr[1]),
166 .data(data[1]),
167 .clk(clk),
168 .wr(wr[1]),
169 .rd(rd[1]));
170
a85b19a7 171 ROM rom(
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172 .address(addr[0]),
173 .data(data[0]),
a85b19a7 174 .clk(clk),
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175 .wr(wr[0]),
176 .rd(rd[0]));
a85b19a7 177
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178 wire lcdhs, lcdvs, lcdclk;
179 wire [2:0] lcdr, lcdg;
180 wire [1:0] lcdb;
181
537e1f83 182 LCDC lcdc(
537e1f83 183 .clk(clk),
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184 .addr(addr[0]),
185 .data(data[0]),
186 .wr(wr[0]),
187 .rd(rd[0]),
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188 .lcdcirq(lcdcirq),
189 .vblankirq(vblankirq),
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190 .lcdclk(lcdclk),
191 .lcdhs(lcdhs),
192 .lcdvs(lcdvs),
193 .lcdr(lcdr),
194 .lcdg(lcdg),
195 .lcdb(lcdb));
196
197 Framebuffer fb(
198 .lcdclk(lcdclk),
199 .lcdhs(lcdhs),
200 .lcdvs(lcdvs),
201 .lcdr(lcdr),
202 .lcdg(lcdg),
203 .lcdb(lcdb),
204 .vgaclk(vgaclk),
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205 .vgahs(hs),
206 .vgavs(vs),
207 .vgar(r),
208 .vgag(g),
209 .vgab(b));
537e1f83 210
a85b19a7 211 AddrMon amon(
eb0f2fe1 212 .clk(clk),
91c74a3f 213 .addr(addr[0]),
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214 .digit(digits),
215 .out(seven),
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216 .freeze(buttons[0]),
217 .periods(
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218 (state == 2'b00) ? 4'b0010 :
219 (state == 2'b01) ? 4'b0001 :
220 (state == 2'b10) ? 4'b1000 :
221 4'b0100) );
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222
223 Switches sw(
a85b19a7 224 .clk(clk),
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225 .address(addr[0]),
226 .data(data[0]),
227 .wr(wr[0]),
228 .rd(rd[0]),
a85b19a7 229 .ledout(leds),
fc443a4f 230 .switches(switches)
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231 );
232
06ad3a30 233 UART nouart ( /* no u */
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234 .clk(clk),
235 .addr(addr[0]),
236 .data(data[0]),
237 .wr(wr[0]),
238 .rd(rd[0]),
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239 .serial(serio)
240 );
9aa931d1 241
eb0f2fe1 242 InternalRAM ram(
9aa931d1 243 .clk(clk),
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244 .address(addr[0]),
245 .data(data[0]),
246 .wr(wr[0]),
247 .rd(rd[0])
eb0f2fe1 248 );
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249
250 MiniRAM mram(
6bd4619b 251 .clk(clk),
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252 .address(addr[1]),
253 .data(data[1]),
254 .wr(wr[1]),
255 .rd(rd[1])
6bd4619b 256 );
06ad3a30 257
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258 Timer tmr(
259 .clk(clk),
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260 .addr(addr[0]),
261 .data(data[0]),
262 .wr(wr[0]),
263 .rd(rd[0]),
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264 .irq(tmrirq)
265 );
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266
267 Interrupt intr(
268 .clk(clk),
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269 .addr(addr[0]),
270 .data(data[0]),
271 .wr(wr[0]),
272 .rd(rd[0]),
00573fd5 273 .vblank(vblankirq),
537e1f83 274 .lcdc(lcdcirq),
06ad3a30 275 .tovf(tmrirq),
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276 .serial(1'b0),
277 .buttons(1'b0),
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278 .master(irq),
279 .jaddr(jaddr));
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280
281 Soundcore sound(
282 .core_clk(clk),
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283 .addr(addr[0]),
284 .data(data[0]),
285 .rd(rd[0]),
286 .wr(wr[0]),
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287 .snd_data_l(soundl),
288 .snd_data_r(soundr));
a85b19a7 289endmodule
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