Add isim to makefile
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
fe3dc890 9 reg [7:0] rom [1023:0];
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10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
fe3dc890 13 wire [7:0] odata = rom[address[10:0]];
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14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
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18module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] ram [127:0];
25
26 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27 reg [7:0] odata;
28 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29
30 always @(negedge clk)
31 begin
32 if (decode) // This has to go this way. The only way XST knows how to do
33 begin // block ram is chip select, write enable, and always
34 if (wr) // reading. "else if rd" does not cut it ...
35 ram[address[6:0]] <= data;
36 odata <= ram[address[6:0]];
37 end
38 end
c279b666 39endmodule
6bd4619b 40
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41module InternalRAM(
42 input [15:0] address,
43 inout [7:0] data,
44 input clk,
45 input wr, rd);
46
fe3dc890 47 // synthesis attribute ram_style of ram is block
616eebe0 48 reg [7:0] ram [8191:0];
a85b19a7 49
c87db60a 50 wire decode = address[15:13] == 3'b110;
a85b19a7 51 reg [7:0] odata;
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52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
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56 if (decode) // This has to go this way. The only way XST knows how to do
57 begin // block ram is chip select, write enable, and always
58 if (wr) // reading. "else if rd" does not cut it ...
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59 ram[address[12:0]] <= data;
60 odata <= ram[address[12:0]];
c87db60a 61 end
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62 end
63endmodule
64
65module Switches(
66 input [15:0] address,
67 inout [7:0] data,
68 input clk,
69 input wr, rd,
70 input [7:0] switches,
9c834ff2 71 output reg [7:0] ledout = 0);
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72
73 wire decode = address == 16'hFF51;
74 reg [7:0] odata;
75 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
76
77 always @(negedge clk)
78 begin
79 if (decode && rd)
80 odata <= switches;
81 else if (decode && wr)
82 ledout <= data;
83 end
84endmodule
85
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86`ifdef isim
87module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
88endmodule
89`endif
90
a85b19a7 91module CoreTop(
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92`ifdef isim
93 output reg vgaclk = 0,
94 output reg clk = 0,
95`else
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96 input xtal,
97 input [7:0] switches,
ff7fd7f2 98 input [3:0] buttons,
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99 output wire [7:0] leds,
100 output serio,
101 output wire [3:0] digits,
00573fd5 102 output wire [7:0] seven,
e7fb589a 103`endif
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104 output wire hs, vs,
105 output wire [2:0] r, g,
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106 output wire [1:0] b,
107 output wire soundl, soundr);
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108
109`ifdef isim
110 always #62 clk <= ~clk;
111 always #100 vgaclk <= ~vgaclk;
112
113 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 114
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115 wire [7:0] leds;
116 wire serio;
117 wire [3:0] digits;
118 wire [7:0] seven;
119 wire [7:0] switches = 8'b0;
120 wire [3:0] buttons = 4'b0;
121`else
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122 wire xtalb, clk, vgaclk;
123 IBUFG iclkbuf(.O(xtalb), .I(xtal));
124 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
125 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
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126`endif
127
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128 wire [15:0] addr;
129 wire [7:0] data;
130 wire wr, rd;
f8db6448 131
00573fd5 132 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 133 wire [7:0] jaddr;
6c46357c 134 wire [1:0] state;
179b4347 135
a85b19a7 136 GBZ80Core core(
179b4347 137 .clk(clk),
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138 .busaddress(addr),
139 .busdata(data),
140 .buswr(wr),
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141 .busrd(rd),
142 .irq(irq),
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143 .jaddr(jaddr),
144 .state(state));
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145
146 ROM rom(
147 .address(addr),
148 .data(data),
149 .clk(clk),
150 .wr(wr),
151 .rd(rd));
152
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153 wire lcdhs, lcdvs, lcdclk;
154 wire [2:0] lcdr, lcdg;
155 wire [1:0] lcdb;
156
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157 LCDC lcdc(
158 .addr(addr),
159 .data(data),
160 .clk(clk),
161 .wr(wr),
162 .rd(rd),
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163 .lcdcirq(lcdcirq),
164 .vblankirq(vblankirq),
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165 .lcdclk(lcdclk),
166 .lcdhs(lcdhs),
167 .lcdvs(lcdvs),
168 .lcdr(lcdr),
169 .lcdg(lcdg),
170 .lcdb(lcdb));
171
172 Framebuffer fb(
173 .lcdclk(lcdclk),
174 .lcdhs(lcdhs),
175 .lcdvs(lcdvs),
176 .lcdr(lcdr),
177 .lcdg(lcdg),
178 .lcdb(lcdb),
179 .vgaclk(vgaclk),
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180 .vgahs(hs),
181 .vgavs(vs),
182 .vgar(r),
183 .vgag(g),
184 .vgab(b));
537e1f83 185
a85b19a7 186 AddrMon amon(
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187 .addr(addr),
188 .clk(clk),
189 .digit(digits),
190 .out(seven),
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191 .freeze(buttons[0]),
192 .periods(
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193 (state == 2'b00) ? 4'b0010 :
194 (state == 2'b01) ? 4'b0001 :
195 (state == 2'b10) ? 4'b1000 :
196 4'b0100) );
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197
198 Switches sw(
199 .address(addr),
200 .data(data),
201 .clk(clk),
202 .wr(wr),
203 .rd(rd),
204 .ledout(leds),
fc443a4f 205 .switches(switches)
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206 );
207
06ad3a30 208 UART nouart ( /* no u */
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209 .clk(clk),
210 .wr(wr),
211 .rd(rd),
212 .addr(addr),
213 .data(data),
214 .serial(serio)
215 );
9aa931d1 216
eb0f2fe1 217 InternalRAM ram(
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218 .address(addr),
219 .data(data),
220 .clk(clk),
221 .wr(wr),
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222 .rd(rd)
223 );
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224
225 MiniRAM mram(
226 .address(addr),
227 .data(data),
228 .clk(clk),
229 .wr(wr),
230 .rd(rd)
231 );
06ad3a30 232
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233 Timer tmr(
234 .clk(clk),
235 .wr(wr),
236 .rd(rd),
237 .addr(addr),
238 .data(data),
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239 .irq(tmrirq)
240 );
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241
242 Interrupt intr(
243 .clk(clk),
244 .rd(rd),
245 .wr(wr),
246 .addr(addr),
247 .data(data),
00573fd5 248 .vblank(vblankirq),
537e1f83 249 .lcdc(lcdcirq),
06ad3a30 250 .tovf(tmrirq),
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251 .serial(1'b0),
252 .buttons(1'b0),
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253 .master(irq),
254 .jaddr(jaddr));
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255
256 Soundcore sound(
257 .core_clk(clk),
258 .rd(rd),
259 .wr(wr),
260 .addr(addr),
261 .data(data),
262 .snd_data_l(soundl),
263 .snd_data_r(soundr));
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264endmodule
265
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266`ifdef verilator
267`else
a85b19a7 268module TestBench();
62940da0 269 reg clk = 1;
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270 wire [15:0] addr;
271 wire [7:0] data;
272 wire wr, rd;
273
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274 wire irq, tmrirq;
275 wire [7:0] jaddr;
276
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277 wire [7:0] leds;
278 wire [7:0] switches;
a85b19a7 279
179b4347 280 always #62 clk <= ~clk;
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281 GBZ80Core core(
282 .clk(clk),
283 .busaddress(addr),
284 .busdata(data),
285 .buswr(wr),
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286 .busrd(rd),
287 .irq(irq),
288 .jaddr(jaddr));
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289
290 ROM rom(
291 .clk(clk),
292 .address(addr),
293 .data(data),
294 .wr(wr),
295 .rd(rd));
296
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297 InternalRAM ram(
298 .address(addr),
299 .data(data),
300 .clk(clk),
301 .wr(wr),
302 .rd(rd));
a85b19a7 303
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304 wire serio;
305 UART uart(
306 .addr(addr),
307 .data(data),
308 .clk(clk),
309 .wr(wr),
310 .rd(rd),
311 .serial(serio));
a85b19a7 312
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313 Timer tmr(
314 .clk(clk),
315 .wr(wr),
316 .rd(rd),
317 .addr(addr),
318 .data(data),
319 .irq(tmrirq));
320
321 Interrupt intr(
322 .clk(clk),
323 .rd(rd),
324 .wr(wr),
325 .addr(addr),
326 .data(data),
327 .vblank(0),
328 .lcdc(0),
329 .tovf(tmrirq),
330 .serial(0),
331 .buttons(0),
332 .master(irq),
333 .jaddr(jaddr));
334
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335 Switches sw(
336 .clk(clk),
337 .address(addr),
338 .data(data),
339 .wr(wr),
340 .rd(rd),
341 .switches(switches),
342 .ledout(leds));
a85b19a7 343endmodule
e7fb589a 344`endif
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