Fix bug in UART where idle state is not entered by default
[fpgaboy.git] / System.v
CommitLineData
a85b19a7
JW
1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] ram [8191:0];
25
9aa931d1 26 wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
a85b19a7
JW
27 reg [7:0] odata;
28 wire idata = data;
29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
33 if (decode && rd)
34 odata <= ram[address[12:0]];
35 else if (decode && wr)
36 ram[address[12:0]] <= data;
37 end
38endmodule
39
40module Switches(
41 input [15:0] address,
42 inout [7:0] data,
43 input clk,
44 input wr, rd,
45 input [7:0] switches,
46 output reg [7:0] ledout);
47
48 wire decode = address == 16'hFF51;
49 reg [7:0] odata;
50 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
51
52 always @(negedge clk)
53 begin
54 if (decode && rd)
55 odata <= switches;
56 else if (decode && wr)
57 ledout <= data;
58 end
59endmodule
60
61module CoreTop(
62 input xtal,
63 input [7:0] switches,
64 output wire [7:0] leds,
65 output serio,
66 output wire [3:0] digits,
67 output wire [7:0] seven);
68
69 wire clk;
70 //IBUFG ibuf (.O(clk), .I(iclk));
71
72 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
73
74 wire [15:0] addr;
75 wire [7:0] data;
76 wire wr, rd;
77
78 GBZ80Core core(
79 .clk(clk),
80 .busaddress(addr),
81 .busdata(data),
82 .buswr(wr),
83 .busrd(rd));
84
85 ROM rom(
86 .address(addr),
87 .data(data),
88 .clk(clk),
89 .wr(wr),
90 .rd(rd));
91
92 AddrMon amon(
93 .addr(addr),
94 .clk(clk),
95 .digit(digits),
96 .out(seven)
97 );
98
99 Switches sw(
100 .address(addr),
101 .data(data),
102 .clk(clk),
103 .wr(wr),
104 .rd(rd),
105 .ledout(leds),
106 .switches(switches)
107 );
108
109 UART nouart (
110 .clk(clk),
111 .wr(wr),
112 .rd(rd),
113 .addr(addr),
114 .data(data),
115 .serial(serio)
116 );
9aa931d1
JW
117
118 InternalRAM ram(
119 .address(addr),
120 .data(data),
121 .clk(clk),
122 .wr(wr),
123 .rd(rd));
a85b19a7
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124endmodule
125
126module TestBench();
127 reg clk = 0;
128 wire [15:0] addr;
129 wire [7:0] data;
130 wire wr, rd;
131
132// wire [7:0] leds;
133// wire [7:0] switches;
134
135 always #10 clk <= ~clk;
136 GBZ80Core core(
137 .clk(clk),
138 .busaddress(addr),
139 .busdata(data),
140 .buswr(wr),
141 .busrd(rd));
142
143 ROM rom(
144 .clk(clk),
145 .address(addr),
146 .data(data),
147 .wr(wr),
148 .rd(rd));
149
9aa931d1
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150 InternalRAM ram(
151 .address(addr),
152 .data(data),
153 .clk(clk),
154 .wr(wr),
155 .rd(rd));
a85b19a7 156
6493be2b
JW
157 wire serio;
158 UART uart(
159 .addr(addr),
160 .data(data),
161 .clk(clk),
162 .wr(wr),
163 .rd(rd),
164 .serial(serio));
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165
166// Switches sw(
167// .clk(clk),
168// .address(addr),
169// .data(data),
170// .wr(wr),
171// .rd(rd),
172// .switches(switches),
173// .leds(leds));
174endmodule
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