Fix bug in UART where idle state is not entered by default

[fpgaboy.git] / System.v

`timescale 1ns / 1ps
module ROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg [7:0] rom [2047:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	wire [7:0] odata = rom[address[11:0]];
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	//assign data = rd ? odata : 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [8191:0];
	
	wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
	reg [7:0] odata;
	wire idata = data;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(negedge clk)
	begin
		if (decode && rd)
			odata <= ram[address[12:0]];
		else if (decode && wr)
			ram[address[12:0]] <= data;
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
	
	always @(negedge clk)
	begin
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

module CoreTop(
	input xtal,
	input [7:0] switches,
	output wire [7:0] leds,
	output serio,
	output wire [3:0] digits,
	output wire [7:0] seven);
	
	wire clk;
	//IBUFG ibuf (.O(clk), .I(iclk));
	
	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));

	wire [15:0] addr;	
	wire [7:0] data;
	wire wr, rd;

	GBZ80Core core(
		.clk(clk),
		.busaddress(addr),
		.busdata(data),
		.buswr(wr),
		.busrd(rd));
	
	ROM rom(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd));
	
	AddrMon amon(
    .addr(addr), 
    .clk(clk), 
    .digit(digits), 
    .out(seven)
    );
	 
	Switches sw(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.ledout(leds),
		.switches(switches)
		);

	UART nouart (
    .clk(clk), 
    .wr(wr), 
    .rd(rd), 
    .addr(addr), 
    .data(data), 
    .serial(serio)
    );

  InternalRAM ram(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd));
endmodule

module TestBench();
	reg clk = 0;
	wire [15:0] addr;
	wire [7:0] data;
	wire wr, rd;
	
//	wire [7:0] leds;
//	wire [7:0] switches;
	
	always #10 clk <= ~clk;
	GBZ80Core core(
		.clk(clk),
		.busaddress(addr),
		.busdata(data),
		.buswr(wr),
		.busrd(rd));
	
	ROM rom(
		.clk(clk),
		.address(addr),
		.data(data),
		.wr(wr),
		.rd(rd));
	
	InternalRAM ram(
		.address(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd));

	wire serio;
	UART uart(
		.addr(addr),
		.data(data),
		.clk(clk),
		.wr(wr),
		.rd(rd),
		.serial(serio));
	
//	Switches sw(
//		.clk(clk),
//		.address(addr),
//		.data(data),
//		.wr(wr),
//		.rd(rd),
//		.switches(switches),
//		.leds(leds));
endmodule