Peripherals now have internal latches.
[fpgaboy.git] / System.v
CommitLineData
a85b19a7
JW
1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
a8f4468d 9 reg rdlatch = 0;
2854e399
JW
10 reg [7:0] odata;
11
91c74a3f 12 // synthesis attribute ram_style of rom is block
fe3dc890 13 reg [7:0] rom [1023:0];
a85b19a7
JW
14 initial $readmemh("rom.hex", rom);
15
16 wire decode = address[15:13] == 0;
a8f4468d
JW
17 always @(posedge clk) begin
18 rdlatch <= rd && decode;
2854e399 19 odata <= rom[address[10:0]];
a8f4468d
JW
20 end
21 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7
JW
22endmodule
23
91c74a3f
JW
24module BootstrapROM(
25 input [15:0] address,
26 inout [7:0] data,
27 input clk,
28 input wr, rd);
29
a8f4468d 30 reg rdlatch = 0;
2854e399
JW
31 reg [7:0] brom [255:0];
32 initial $readmemh("bootstrap.hex", brom);
91c74a3f
JW
33
34 wire decode = address[15:8] == 0;
2854e399 35 wire [7:0] odata = brom[address[7:0]];
a8f4468d
JW
36 always @(posedge clk)
37 rdlatch <= rd && decode;
38 assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f
JW
39endmodule
40
41module MiniRAM(
6bd4619b
JW
42 input [15:0] address,
43 inout [7:0] data,
44 input clk,
45 input wr, rd);
46
47 reg [7:0] ram [127:0];
48
49 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d 50 reg rdlatch = 0;
6bd4619b 51 reg [7:0] odata;
a8f4468d 52 assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b 53
68ce013e 54 always @(posedge clk)
6bd4619b 55 begin
a8f4468d
JW
56 rdlatch <= rd && decode;
57 if (decode) // This has to go this way. The only way XST knows how to do
58 begin // block ram is chip select, write enable, and always
6bd4619b
JW
59 if (wr) // reading. "else if rd" does not cut it ...
60 ram[address[6:0]] <= data;
61 odata <= ram[address[6:0]];
62 end
63 end
c279b666 64endmodule
6bd4619b 65
74610a87
JW
66module CellularRAM(
67 input clk,
68 input [15:0] address,
69 inout [7:0] data,
70 input wr, rd,
71 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
72 output wire [22:0] cr_A,
73 inout [15:0] cr_DQ);
74
75 parameter ADDR_PROGADDRH = 16'hFF60;
76 parameter ADDR_PROGADDRM = 16'hFF61;
77 parameter ADDR_PROGADDRL = 16'hFF62;
78 parameter ADDR_PROGDATA = 16'hFF63;
79
a8f4468d
JW
80 reg rdlatch = 0, wrlatch = 0;
81 reg [15:0] addrlatch = 0;
82 reg [7:0] datalatch = 0;
83
74610a87
JW
84 reg [7:0] progaddrh, progaddrm, progaddrl;
85
86 assign cr_nADV = 0; /* Addresses are always valid! :D */
87 assign cr_nCE = 0; /* The chip is enabled */
88 assign cr_nLB = 0; /* Lower byte is enabled */
89 assign cr_nUB = 0; /* Upper byte is enabled */
90 assign cr_CRE = 0; /* Data writes, not config */
91 assign cr_CLK = 0; /* Clock? I think not! */
92
a8f4468d 93 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
74610a87 94
a8f4468d
JW
95 assign cr_nOE = decode ? ~rdlatch : 1;
96 assign cr_nWE = decode ? ~wrlatch : 1;
74610a87 97
a8f4468d
JW
98 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
99 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
100 (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
101 (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
74610a87
JW
102 23'b0;
103
104 reg [7:0] regbuf;
105
a8f4468d 106 always @(posedge clk) begin
74610a87
JW
107 case (address)
108 ADDR_PROGADDRH: if (wr) progaddrh <= data;
109 ADDR_PROGADDRM: if (wr) progaddrm <= data;
110 ADDR_PROGADDRL: if (wr) progaddrl <= data;
111 endcase
a8f4468d
JW
112 rdlatch <= rd;
113 wrlatch <= wr;
114 addrlatch <= address;
115 datalatch <= data;
116 end
74610a87 117
a8f4468d
JW
118 assign data = (rdlatch && decode) ?
119 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
120 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
121 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87
JW
122 cr_DQ
123 : 8'bzzzzzzzz;
124endmodule
125
a85b19a7
JW
126module InternalRAM(
127 input [15:0] address,
128 inout [7:0] data,
129 input clk,
130 input wr, rd);
131
fe3dc890 132 // synthesis attribute ram_style of ram is block
616eebe0 133 reg [7:0] ram [8191:0];
a85b19a7 134
74610a87 135 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7 136 reg [7:0] odata;
a8f4468d
JW
137 reg rdlatch = 0;
138 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 139
68ce013e 140 always @(posedge clk)
a85b19a7 141 begin
a8f4468d 142 rdlatch <= rd && decode;
74610a87
JW
143 if (decode) // This has to go this way. The only way XST knows how to do
144 begin // block ram is chip select, write enable, and always
95143d64 145 if (wr) // reading. "else if rd" does not cut it ...
616eebe0
JW
146 ram[address[12:0]] <= data;
147 odata <= ram[address[12:0]];
c87db60a 148 end
a85b19a7
JW
149 end
150endmodule
151
152module Switches(
153 input [15:0] address,
154 inout [7:0] data,
155 input clk,
156 input wr, rd,
157 input [7:0] switches,
9c834ff2 158 output reg [7:0] ledout = 0);
a85b19a7
JW
159
160 wire decode = address == 16'hFF51;
161 reg [7:0] odata;
a8f4468d
JW
162 reg rdlatch = 0;
163 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 164
68ce013e 165 always @(posedge clk)
a85b19a7 166 begin
a8f4468d 167 rdlatch <= rd && decode;
a85b19a7
JW
168 if (decode && rd)
169 odata <= switches;
170 else if (decode && wr)
171 ledout <= data;
172 end
173endmodule
174
e7fb589a
JW
175`ifdef isim
176module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
177endmodule
178`endif
179
a85b19a7 180module CoreTop(
e7fb589a
JW
181`ifdef isim
182 output reg vgaclk = 0,
183 output reg clk = 0,
184`else
a85b19a7
JW
185 input xtal,
186 input [7:0] switches,
ff7fd7f2 187 input [3:0] buttons,
a85b19a7
JW
188 output wire [7:0] leds,
189 output serio,
190 output wire [3:0] digits,
00573fd5 191 output wire [7:0] seven,
74610a87
JW
192 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
193 output wire [22:0] cr_A,
194 inout [15:0] cr_DQ,
e7fb589a 195`endif
00573fd5
JW
196 output wire hs, vs,
197 output wire [2:0] r, g,
09c1936c
JW
198 output wire [1:0] b,
199 output wire soundl, soundr);
e7fb589a
JW
200
201`ifdef isim
202 always #62 clk <= ~clk;
203 always #100 vgaclk <= ~vgaclk;
204
205 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 206
e7fb589a
JW
207 wire [7:0] leds;
208 wire serio;
209 wire [3:0] digits;
210 wire [7:0] seven;
211 wire [7:0] switches = 8'b0;
212 wire [3:0] buttons = 4'b0;
213`else
fe3dc890
JW
214 wire xtalb, clk, vgaclk;
215 IBUFG iclkbuf(.O(xtalb), .I(xtal));
216 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
217 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a
JW
218`endif
219
91c74a3f
JW
220 wire [15:0] addr [1:0];
221 wire [7:0] data [1:0];
222 wire wr [1:0], rd [1:0];
f8db6448 223
00573fd5 224 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 225 wire [7:0] jaddr;
6c46357c 226 wire [1:0] state;
179b4347 227
a85b19a7 228 GBZ80Core core(
179b4347 229 .clk(clk),
91c74a3f
JW
230 .bus0address(addr[0]),
231 .bus0data(data[0]),
232 .bus0wr(wr[0]),
233 .bus0rd(rd[0]),
234 .bus1address(addr[1]),
235 .bus1data(data[1]),
236 .bus1wr(wr[1]),
237 .bus1rd(rd[1]),
f8db6448 238 .irq(irq),
6c46357c
JW
239 .jaddr(jaddr),
240 .state(state));
a85b19a7 241
91c74a3f
JW
242 BootstrapROM brom(
243 .address(addr[1]),
244 .data(data[1]),
245 .clk(clk),
246 .wr(wr[1]),
247 .rd(rd[1]));
248
74610a87 249`ifdef isim
a85b19a7 250 ROM rom(
91c74a3f
JW
251 .address(addr[0]),
252 .data(data[0]),
a85b19a7 253 .clk(clk),
91c74a3f
JW
254 .wr(wr[0]),
255 .rd(rd[0]));
74610a87
JW
256`else
257 CellularRAM cellram(
258 .address(addr[0]),
259 .data(data[0]),
260 .clk(clk),
261 .wr(wr[0]),
262 .rd(rd[0])
263 .cr_nADV(cr_nADV),
264 .cr_nCE(cr_nCE),
265 .cr_nOE(cr_nOE),
266 .cr_nWR(cr_nWE),
267 .cr_CRE(cr_CRE),
268 .cr_nLB(cr_nLB),
269 .cr_nUB(cr_nUB),
270 .cr_CLK(cr_CLK),
271 .cr_A(cr_A),
272 .cr_DQ(cr_DQ));
273`endif
a85b19a7 274
fe3dc890
JW
275 wire lcdhs, lcdvs, lcdclk;
276 wire [2:0] lcdr, lcdg;
277 wire [1:0] lcdb;
278
537e1f83 279 LCDC lcdc(
537e1f83 280 .clk(clk),
91c74a3f
JW
281 .addr(addr[0]),
282 .data(data[0]),
283 .wr(wr[0]),
284 .rd(rd[0]),
00573fd5
JW
285 .lcdcirq(lcdcirq),
286 .vblankirq(vblankirq),
fe3dc890
JW
287 .lcdclk(lcdclk),
288 .lcdhs(lcdhs),
289 .lcdvs(lcdvs),
290 .lcdr(lcdr),
291 .lcdg(lcdg),
292 .lcdb(lcdb));
293
294 Framebuffer fb(
295 .lcdclk(lcdclk),
296 .lcdhs(lcdhs),
297 .lcdvs(lcdvs),
298 .lcdr(lcdr),
299 .lcdg(lcdg),
300 .lcdb(lcdb),
301 .vgaclk(vgaclk),
00573fd5
JW
302 .vgahs(hs),
303 .vgavs(vs),
304 .vgar(r),
305 .vgag(g),
306 .vgab(b));
537e1f83 307
a85b19a7 308 AddrMon amon(
eb0f2fe1 309 .clk(clk),
91c74a3f 310 .addr(addr[0]),
eb0f2fe1
JW
311 .digit(digits),
312 .out(seven),
6c46357c
JW
313 .freeze(buttons[0]),
314 .periods(
179b4347
JW
315 (state == 2'b00) ? 4'b0010 :
316 (state == 2'b01) ? 4'b0001 :
317 (state == 2'b10) ? 4'b1000 :
318 4'b0100) );
a85b19a7
JW
319
320 Switches sw(
a85b19a7 321 .clk(clk),
91c74a3f
JW
322 .address(addr[0]),
323 .data(data[0]),
324 .wr(wr[0]),
325 .rd(rd[0]),
a85b19a7 326 .ledout(leds),
fc443a4f 327 .switches(switches)
a85b19a7
JW
328 );
329
06ad3a30 330 UART nouart ( /* no u */
91c74a3f
JW
331 .clk(clk),
332 .addr(addr[0]),
333 .data(data[0]),
334 .wr(wr[0]),
335 .rd(rd[0]),
eb0f2fe1
JW
336 .serial(serio)
337 );
9aa931d1 338
eb0f2fe1 339 InternalRAM ram(
9aa931d1 340 .clk(clk),
91c74a3f
JW
341 .address(addr[0]),
342 .data(data[0]),
343 .wr(wr[0]),
344 .rd(rd[0])
eb0f2fe1 345 );
6bd4619b
JW
346
347 MiniRAM mram(
6bd4619b 348 .clk(clk),
91c74a3f
JW
349 .address(addr[1]),
350 .data(data[1]),
351 .wr(wr[1]),
352 .rd(rd[1])
6bd4619b 353 );
06ad3a30 354
06ad3a30
JW
355 Timer tmr(
356 .clk(clk),
91c74a3f
JW
357 .addr(addr[0]),
358 .data(data[0]),
359 .wr(wr[0]),
360 .rd(rd[0]),
eb0f2fe1
JW
361 .irq(tmrirq)
362 );
06ad3a30
JW
363
364 Interrupt intr(
365 .clk(clk),
91c74a3f
JW
366 .addr(addr[0]),
367 .data(data[0]),
368 .wr(wr[0]),
369 .rd(rd[0]),
00573fd5 370 .vblank(vblankirq),
537e1f83 371 .lcdc(lcdcirq),
06ad3a30 372 .tovf(tmrirq),
e7fb589a
JW
373 .serial(1'b0),
374 .buttons(1'b0),
06ad3a30
JW
375 .master(irq),
376 .jaddr(jaddr));
09c1936c
JW
377
378 Soundcore sound(
379 .core_clk(clk),
91c74a3f
JW
380 .addr(addr[0]),
381 .data(data[0]),
382 .rd(rd[0]),
383 .wr(wr[0]),
09c1936c
JW
384 .snd_data_l(soundl),
385 .snd_data_r(soundr));
a85b19a7 386endmodule
This page took 0.065001 seconds and 4 git commands to generate.