Yaaay, everything is posedge now
[fpgaboy.git] / System.v
CommitLineData
a85b19a7
JW
1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
2854e399
JW
9 reg [7:0] odata;
10
91c74a3f 11 // synthesis attribute ram_style of rom is block
fe3dc890 12 reg [7:0] rom [1023:0];
a85b19a7
JW
13 initial $readmemh("rom.hex", rom);
14
15 wire decode = address[15:13] == 0;
2854e399
JW
16 always @(posedge clk)
17 odata <= rom[address[10:0]];
a85b19a7 18 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
a85b19a7
JW
19endmodule
20
91c74a3f
JW
21module BootstrapROM(
22 input [15:0] address,
23 inout [7:0] data,
24 input clk,
25 input wr, rd);
26
2854e399
JW
27 reg [7:0] brom [255:0];
28 initial $readmemh("bootstrap.hex", brom);
91c74a3f
JW
29
30 wire decode = address[15:8] == 0;
2854e399 31 wire [7:0] odata = brom[address[7:0]];
91c74a3f
JW
32 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
33endmodule
34
35module MiniRAM(
6bd4619b
JW
36 input [15:0] address,
37 inout [7:0] data,
38 input clk,
39 input wr, rd);
40
41 reg [7:0] ram [127:0];
42
43 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
44 reg [7:0] odata;
45 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
46
68ce013e 47 always @(posedge clk)
6bd4619b
JW
48 begin
49 if (decode) // This has to go this way. The only way XST knows how to do
50 begin // block ram is chip select, write enable, and always
51 if (wr) // reading. "else if rd" does not cut it ...
52 ram[address[6:0]] <= data;
53 odata <= ram[address[6:0]];
54 end
55 end
c279b666 56endmodule
6bd4619b 57
a85b19a7
JW
58module InternalRAM(
59 input [15:0] address,
60 inout [7:0] data,
61 input clk,
62 input wr, rd);
63
fe3dc890 64 // synthesis attribute ram_style of ram is block
616eebe0 65 reg [7:0] ram [8191:0];
a85b19a7 66
c87db60a 67 wire decode = address[15:13] == 3'b110;
a85b19a7 68 reg [7:0] odata;
a85b19a7
JW
69 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
70
68ce013e 71 always @(posedge clk)
a85b19a7 72 begin
95143d64
JW
73 if (decode) // This has to go this way. The only way XST knows how to do
74 begin // block ram is chip select, write enable, and always
75 if (wr) // reading. "else if rd" does not cut it ...
616eebe0
JW
76 ram[address[12:0]] <= data;
77 odata <= ram[address[12:0]];
c87db60a 78 end
a85b19a7
JW
79 end
80endmodule
81
82module Switches(
83 input [15:0] address,
84 inout [7:0] data,
85 input clk,
86 input wr, rd,
87 input [7:0] switches,
9c834ff2 88 output reg [7:0] ledout = 0);
a85b19a7
JW
89
90 wire decode = address == 16'hFF51;
91 reg [7:0] odata;
92 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
93
68ce013e 94 always @(posedge clk)
a85b19a7
JW
95 begin
96 if (decode && rd)
97 odata <= switches;
98 else if (decode && wr)
99 ledout <= data;
100 end
101endmodule
102
e7fb589a
JW
103`ifdef isim
104module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
105endmodule
106`endif
107
a85b19a7 108module CoreTop(
e7fb589a
JW
109`ifdef isim
110 output reg vgaclk = 0,
111 output reg clk = 0,
112`else
a85b19a7
JW
113 input xtal,
114 input [7:0] switches,
ff7fd7f2 115 input [3:0] buttons,
a85b19a7
JW
116 output wire [7:0] leds,
117 output serio,
118 output wire [3:0] digits,
00573fd5 119 output wire [7:0] seven,
e7fb589a 120`endif
00573fd5
JW
121 output wire hs, vs,
122 output wire [2:0] r, g,
09c1936c
JW
123 output wire [1:0] b,
124 output wire soundl, soundr);
e7fb589a
JW
125
126`ifdef isim
127 always #62 clk <= ~clk;
128 always #100 vgaclk <= ~vgaclk;
129
130 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 131
e7fb589a
JW
132 wire [7:0] leds;
133 wire serio;
134 wire [3:0] digits;
135 wire [7:0] seven;
136 wire [7:0] switches = 8'b0;
137 wire [3:0] buttons = 4'b0;
138`else
fe3dc890
JW
139 wire xtalb, clk, vgaclk;
140 IBUFG iclkbuf(.O(xtalb), .I(xtal));
141 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
142 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a
JW
143`endif
144
91c74a3f
JW
145 wire [15:0] addr [1:0];
146 wire [7:0] data [1:0];
147 wire wr [1:0], rd [1:0];
f8db6448 148
00573fd5 149 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 150 wire [7:0] jaddr;
6c46357c 151 wire [1:0] state;
179b4347 152
a85b19a7 153 GBZ80Core core(
179b4347 154 .clk(clk),
91c74a3f
JW
155 .bus0address(addr[0]),
156 .bus0data(data[0]),
157 .bus0wr(wr[0]),
158 .bus0rd(rd[0]),
159 .bus1address(addr[1]),
160 .bus1data(data[1]),
161 .bus1wr(wr[1]),
162 .bus1rd(rd[1]),
f8db6448 163 .irq(irq),
6c46357c
JW
164 .jaddr(jaddr),
165 .state(state));
a85b19a7 166
91c74a3f
JW
167 BootstrapROM brom(
168 .address(addr[1]),
169 .data(data[1]),
170 .clk(clk),
171 .wr(wr[1]),
172 .rd(rd[1]));
173
a85b19a7 174 ROM rom(
91c74a3f
JW
175 .address(addr[0]),
176 .data(data[0]),
a85b19a7 177 .clk(clk),
91c74a3f
JW
178 .wr(wr[0]),
179 .rd(rd[0]));
a85b19a7 180
fe3dc890
JW
181 wire lcdhs, lcdvs, lcdclk;
182 wire [2:0] lcdr, lcdg;
183 wire [1:0] lcdb;
184
537e1f83 185 LCDC lcdc(
537e1f83 186 .clk(clk),
91c74a3f
JW
187 .addr(addr[0]),
188 .data(data[0]),
189 .wr(wr[0]),
190 .rd(rd[0]),
00573fd5
JW
191 .lcdcirq(lcdcirq),
192 .vblankirq(vblankirq),
fe3dc890
JW
193 .lcdclk(lcdclk),
194 .lcdhs(lcdhs),
195 .lcdvs(lcdvs),
196 .lcdr(lcdr),
197 .lcdg(lcdg),
198 .lcdb(lcdb));
199
200 Framebuffer fb(
201 .lcdclk(lcdclk),
202 .lcdhs(lcdhs),
203 .lcdvs(lcdvs),
204 .lcdr(lcdr),
205 .lcdg(lcdg),
206 .lcdb(lcdb),
207 .vgaclk(vgaclk),
00573fd5
JW
208 .vgahs(hs),
209 .vgavs(vs),
210 .vgar(r),
211 .vgag(g),
212 .vgab(b));
537e1f83 213
a85b19a7 214 AddrMon amon(
eb0f2fe1 215 .clk(clk),
91c74a3f 216 .addr(addr[0]),
eb0f2fe1
JW
217 .digit(digits),
218 .out(seven),
6c46357c
JW
219 .freeze(buttons[0]),
220 .periods(
179b4347
JW
221 (state == 2'b00) ? 4'b0010 :
222 (state == 2'b01) ? 4'b0001 :
223 (state == 2'b10) ? 4'b1000 :
224 4'b0100) );
a85b19a7
JW
225
226 Switches sw(
a85b19a7 227 .clk(clk),
91c74a3f
JW
228 .address(addr[0]),
229 .data(data[0]),
230 .wr(wr[0]),
231 .rd(rd[0]),
a85b19a7 232 .ledout(leds),
fc443a4f 233 .switches(switches)
a85b19a7
JW
234 );
235
06ad3a30 236 UART nouart ( /* no u */
91c74a3f
JW
237 .clk(clk),
238 .addr(addr[0]),
239 .data(data[0]),
240 .wr(wr[0]),
241 .rd(rd[0]),
eb0f2fe1
JW
242 .serial(serio)
243 );
9aa931d1 244
eb0f2fe1 245 InternalRAM ram(
9aa931d1 246 .clk(clk),
91c74a3f
JW
247 .address(addr[0]),
248 .data(data[0]),
249 .wr(wr[0]),
250 .rd(rd[0])
eb0f2fe1 251 );
6bd4619b
JW
252
253 MiniRAM mram(
6bd4619b 254 .clk(clk),
91c74a3f
JW
255 .address(addr[1]),
256 .data(data[1]),
257 .wr(wr[1]),
258 .rd(rd[1])
6bd4619b 259 );
06ad3a30 260
06ad3a30
JW
261 Timer tmr(
262 .clk(clk),
91c74a3f
JW
263 .addr(addr[0]),
264 .data(data[0]),
265 .wr(wr[0]),
266 .rd(rd[0]),
eb0f2fe1
JW
267 .irq(tmrirq)
268 );
06ad3a30
JW
269
270 Interrupt intr(
271 .clk(clk),
91c74a3f
JW
272 .addr(addr[0]),
273 .data(data[0]),
274 .wr(wr[0]),
275 .rd(rd[0]),
00573fd5 276 .vblank(vblankirq),
537e1f83 277 .lcdc(lcdcirq),
06ad3a30 278 .tovf(tmrirq),
e7fb589a
JW
279 .serial(1'b0),
280 .buttons(1'b0),
06ad3a30
JW
281 .master(irq),
282 .jaddr(jaddr));
09c1936c
JW
283
284 Soundcore sound(
285 .core_clk(clk),
91c74a3f
JW
286 .addr(addr[0]),
287 .data(data[0]),
288 .rd(rd[0]),
289 .wr(wr[0]),
09c1936c
JW
290 .snd_data_l(soundl),
291 .snd_data_r(soundr));
a85b19a7 292endmodule
This page took 0.061804 seconds and 4 git commands to generate.