[fpgaboy.git] / System.v


`timescale 1ns / 1ps
module SimROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] odata;

	reg [7:0] rom [32767:0];
	initial $readmemh("rom.hex", rom);

	wire decode = address[15:13] == 0;
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		odata <= rom[address[10:0]];
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module BootstrapROM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);

	reg rdlatch = 0;
	reg [7:0] addrlatch = 0;
	reg romno = 0, romnotmp = 0;
	reg [7:0] brom0 [255:0];
	reg [7:0] brom1 [255:0];
	
	initial $readmemh("fpgaboot.hex", brom0);
	initial $readmemh("gbboot.hex", brom1);
	
`ifdef isim
	initial romno <= 1;
`endif

	wire decode = address[15:8] == 0;
	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
	always @(posedge clk) begin
		rdlatch <= rd && decode;
		addrlatch <= address[7:0];
		if (wr && decode) romnotmp <= data[0];
		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
	end
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	reg [7:0] ram [127:0];
	
	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
	reg rdlatch = 0;
	reg [7:0] odata;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[6:0]] <= data;
			odata <= ram[address[6:0]];
		end
	end
endmodule

module CellularRAM(
	input clk,
	input [15:0] address,
	inout [7:0] data,
	input wr, rd,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ);
	
	parameter ADDR_PROGADDRH = 16'hFF60;
	parameter ADDR_PROGADDRM = 16'hFF61;
	parameter ADDR_PROGADDRL = 16'hFF62;
	parameter ADDR_PROGDATA = 16'hFF63;
	parameter ADDR_MBC = 16'hFF64;
	
	reg rdlatch = 0, wrlatch = 0;
	reg [15:0] addrlatch = 0;
	reg [7:0] datalatch = 0;
	
	reg [7:0] progaddrh, progaddrm, progaddrl;
	
	reg [22:0] progaddr;
	
	reg [7:0] mbc_emul = 8'b00000101;	// High bit is whether we're poking flash
						// low 7 bits are the MBC that we are emulating
	
	assign cr_nADV = 0;	/* Addresses are always valid! :D */
	assign cr_nCE = 0;	/* The chip is enabled */
	assign cr_nLB = 0;	/* Lower byte is enabled */
	assign cr_nUB = 0;	/* Upper byte is enabled */
	assign cr_CRE = 0;	/* Data writes, not config */
	assign cr_CLK = 0;	/* Clock? I think not! */
	
	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
	
	reg [3:0] rambank = 0;
	reg [8:0] rombank = 1;
	
	assign cr_nOE = decode ? ~rdlatch : 1;
	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
	
	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
			(addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
			(addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
			(addrlatch == ADDR_PROGDATA) ? progaddr :
			23'b0;
	
	always @(posedge clk) begin
		case (address)
		ADDR_PROGADDRH: if (wr) progaddrh <= data;
		ADDR_PROGADDRM: if (wr) progaddrm <= data;
		ADDR_PROGADDRL: if (wr) progaddrl <= data;
		ADDR_PROGDATA:	if (rd || wr) begin
					progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
					{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
				end
		ADDR_MBC:	begin
					mbc_emul <= data;
					rambank <= 0;
					rombank <= 1;
				end
		endcase
		
		if (mbc_emul[6:0] == 5) begin
			if ((address[15:12] == 4'h2) && wr)
				rombank <= {rombank[8], data};
			else if ((address[15:12] == 4'h3) && wr)
				rombank <= {data[0], rombank[7:0]};
			else if ((address[15:12] == 4'h4) && wr)
				rambank <= data[3:0];
		end
		
		rdlatch <= rd;
		wrlatch <= wr;
		addrlatch <= address;
		datalatch <= data;
	end
	
	assign data = (rdlatch && decode) ?
				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
				cr_DQ
			: 8'bzzzzzzzz;
endmodule

module InternalRAM(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd);
	
	// synthesis attribute ram_style of ram is block
	reg [7:0] ram [8191:0];
	
	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode)		// This has to go this way. The only way XST knows how to do
		begin			// block ram is chip select, write enable, and always
			if (wr)		// reading. "else if rd" does not cut it ...
				ram[address[12:0]] <= data;
			odata <= ram[address[12:0]];
		end
	end
endmodule

module Switches(
	input [15:0] address,
	inout [7:0] data,
	input clk,
	input wr, rd,
	input [7:0] switches,
	output reg [7:0] ledout = 0);
	
	wire decode = address == 16'hFF51;
	reg [7:0] odata;
	reg rdlatch = 0;
	assign data = rdlatch ? odata : 8'bzzzzzzzz;
	
	always @(posedge clk)
	begin
		rdlatch <= rd && decode;
		if (decode && rd)
			odata <= switches;
		else if (decode && wr)
			ledout <= data;
	end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
	output reg vgaclk = 0,
	output reg clk = 0,
`else
	input xtal,
	input [7:0] switches,
	input [3:0] buttons,
	output wire [7:0] leds,
	output serio,
	input serin,
	output wire [3:0] digits,
	output wire [7:0] seven,
	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	output wire [22:0] cr_A,
	inout [15:0] cr_DQ,
`endif
	output wire hs, vs,
	output wire [2:0] r, g,
	output wire [1:0] b,
	output wire soundl, soundr);

`ifdef isim
	always #62 clk <= ~clk;
	always #100 vgaclk <= ~vgaclk;
	
	Dumpable dump(r,g,b,hs,vs,vgaclk);
	
	wire [7:0] leds;
	wire serio;
	wire serin = 1;
	wire [3:0] digits;
	wire [7:0] seven;
	wire [7:0] switches = 8'b0;
	wire [3:0] buttons = 4'b0;
`else	
	wire xtalb, clk, vgaclk;
	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

	wire [15:0] addr [1:0];
	wire [7:0] data [1:0];
	wire wr [1:0], rd [1:0];
	
	wire irq, tmrirq, lcdcirq, vblankirq;
	wire [7:0] jaddr;
	wire [1:0] state;
	wire ack;
	
	GBZ80Core core(
		.clk(clk),
		.bus0address(addr[0]),
		.bus0data(data[0]),
		.bus0wr(wr[0]),
		.bus0rd(rd[0]),
		.bus1address(addr[1]),
		.bus1data(data[1]),
		.bus1wr(wr[1]),
		.bus1rd(rd[1]),
		.irq(irq),
		.irqack(ack),
		.jaddr(jaddr),
		.state(state));
	
	BootstrapROM brom(
		.address(addr[1]),
		.data(data[1]),
		.clk(clk),
		.wr(wr[1]),
		.rd(rd[1]));
	
`ifdef isim
	SimROM rom(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]));
`else
	CellularRAM cellram(
		.address(addr[0]),
		.data(data[0]),
		.clk(clk),
		.wr(wr[0]),
		.rd(rd[0]),
		.cr_nADV(cr_nADV),
		.cr_nCE(cr_nCE),
		.cr_nOE(cr_nOE),
		.cr_nWE(cr_nWE),
		.cr_CRE(cr_CRE),
		.cr_nLB(cr_nLB),
		.cr_nUB(cr_nUB),
		.cr_CLK(cr_CLK),
		.cr_A(cr_A),
		.cr_DQ(cr_DQ));
`endif
	
	wire lcdhs, lcdvs, lcdclk;
	wire [2:0] lcdr, lcdg;
	wire [1:0] lcdb;
	
	LCDC lcdc(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.lcdcirq(lcdcirq),
		.vblankirq(vblankirq),
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb));
	
	Framebuffer fb(
		.lcdclk(lcdclk),
		.lcdhs(lcdhs),
		.lcdvs(lcdvs),
		.lcdr(lcdr),
		.lcdg(lcdg),
		.lcdb(lcdb),
		.vgaclk(vgaclk),
		.vgahs(hs),
		.vgavs(vs),
		.vgar(r),
		.vgag(g),
		.vgab(b));

	Switches sw(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.ledout(leds),
		.switches(switches)
		);

	AddrMon amon(
		.clk(clk), 
		.addr(addr[0]),
		.digit(digits), 
		.out(seven),
		.freeze(buttons[0]),
		.periods(
			(state == 2'b00) ? 4'b0010 :
			(state == 2'b01) ? 4'b0001 :
			(state == 2'b10) ? 4'b1000 :
			                   4'b0100) );
	 
	UART nouart (	/* no u */
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.serial(serio),
		.serialrx(serin)
		);

	InternalRAM ram(
		.clk(clk),
		.address(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0])
		);
	
	MiniRAM mram(
		.clk(clk),
		.address(addr[1]),
		.data(data[1]),
		.wr(wr[1]),
		.rd(rd[1])
		);

	Timer tmr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.irq(tmrirq)
		);
	
	Interrupt intr(
		.clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.wr(wr[0]),
		.rd(rd[0]),
		.vblank(vblankirq),
		.lcdc(lcdcirq),
		.tovf(tmrirq),
		.serial(1'b0),
		.buttons(1'b0),
		.master(irq),
		.ack(ack),
		.jaddr(jaddr));
	
	Soundcore sound(
		.core_clk(clk),
		.addr(addr[0]),
		.data(data[0]),
		.rd(rd[0]),
		.wr(wr[0]),
		.snd_data_l(soundl),
		.snd_data_r(soundr));
endmodule
Commit	Line	Data
a85b19a7 JW	1
a85b19a7 JW	2	`timescale 1ns / 1ps
6d070aee	3	module SimROM(
a85b19a7 JW	4	input [15:0] address,
	5	inout [7:0] data,
	6	input clk,
	7	input wr, rd);
	8
a8f4468d	9	reg rdlatch = 0;
2854e399 JW	10	reg [7:0] odata;
2854e399 JW	11
6d070aee	12	reg [7:0] rom [32767:0];
a85b19a7 JW	13	initial $readmemh("rom.hex", rom);
	14
	15	wire decode = address[15:13] == 0;
a8f4468d JW	16	always @(posedge clk) begin
a8f4468d JW	17	rdlatch <= rd && decode;
2854e399	18	odata <= rom[address[10:0]];
a8f4468d JW	19	end
a8f4468d JW	20	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 JW	21	endmodule
a85b19a7 JW	22
91c74a3f JW	23	module BootstrapROM(
	24	input [15:0] address,
	25	inout [7:0] data,
	26	input clk,
	27	input wr, rd);
	28
a8f4468d	29	reg rdlatch = 0;
e29171aa	30	reg [7:0] addrlatch = 0;
49c326da JW	31	reg romno = 0, romnotmp = 0;
	32	reg [7:0] brom0 [255:0];
	33	reg [7:0] brom1 [255:0];
	34
	35	initial $readmemh("fpgaboot.hex", brom0);
	36	initial $readmemh("gbboot.hex", brom1);
6d070aee JW	37
	38	`ifdef isim
	39	initial romno <= 1;
	40	`endif
91c74a3f JW	41
91c74a3f JW	42	wire decode = address[15:8] == 0;
49c326da	43	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa	44	always @(posedge clk) begin
a8f4468d	45	rdlatch <= rd && decode;
e29171aa	46	addrlatch <= address[7:0];
49c326da JW	47	if (wr && decode) romnotmp <= data[0];
49c326da JW	48	if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa	49	end
a8f4468d	50	assign data = rdlatch ? odata : 8'bzzzzzzzz;
91c74a3f JW	51	endmodule
	52
	53	module MiniRAM(
6bd4619b JW	54	input [15:0] address,
	55	inout [7:0] data,
	56	input clk,
	57	input wr, rd);
	58
	59	reg [7:0] ram [127:0];
	60
	61	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d	62	reg rdlatch = 0;
6bd4619b	63	reg [7:0] odata;
a8f4468d	64	assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b	65
68ce013e	66	always @(posedge clk)
6bd4619b	67	begin
a8f4468d JW	68	rdlatch <= rd && decode;
	69	if (decode) // This has to go this way. The only way XST knows how to do
	70	begin // block ram is chip select, write enable, and always
6bd4619b JW	71	if (wr) // reading. "else if rd" does not cut it ...
	72	ram[address[6:0]] <= data;
	73	odata <= ram[address[6:0]];
	74	end
	75	end
c279b666	76	endmodule
6bd4619b	77
74610a87 JW	78	module CellularRAM(
	79	input clk,
	80	input [15:0] address,
	81	inout [7:0] data,
	82	input wr, rd,
	83	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	84	output wire [22:0] cr_A,
	85	inout [15:0] cr_DQ);
	86
	87	parameter ADDR_PROGADDRH = 16'hFF60;
	88	parameter ADDR_PROGADDRM = 16'hFF61;
	89	parameter ADDR_PROGADDRL = 16'hFF62;
	90	parameter ADDR_PROGDATA = 16'hFF63;
6d070aee	91	parameter ADDR_MBC = 16'hFF64;
74610a87	92
a8f4468d JW	93	reg rdlatch = 0, wrlatch = 0;
	94	reg [15:0] addrlatch = 0;
	95	reg [7:0] datalatch = 0;
	96
74610a87 JW	97	reg [7:0] progaddrh, progaddrm, progaddrl;
74610a87 JW	98
1eefdc8e JW	99	reg [22:0] progaddr;
1eefdc8e JW	100
6d070aee JW	101	reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash
	102	// low 7 bits are the MBC that we are emulating
	103
74610a87 JW	104	assign cr_nADV = 0; /* Addresses are always valid! :D */
	105	assign cr_nCE = 0; /* The chip is enabled */
	106	assign cr_nLB = 0; /* Lower byte is enabled */
	107	assign cr_nUB = 0; /* Upper byte is enabled */
	108	assign cr_CRE = 0; /* Data writes, not config */
	109	assign cr_CLK = 0; /* Clock? I think not! */
	110
a8f4468d	111	wire decode = (addrlatch[15:14] == 2'b00) /* extrom / \|\| (addrlatch[15:13] == 3'b101) / extram */ \|\| (addrlatch == ADDR_PROGDATA);
74610a87	112
6d070aee JW	113	reg [3:0] rambank = 0;
	114	reg [8:0] rombank = 1;
	115
a8f4468d	116	assign cr_nOE = decode ? ~rdlatch : 1;
6d070aee	117	assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) \|\| (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
74610a87	118
a8f4468d	119	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
6d070aee JW	120	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
	121	(addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
	122	(addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
	123	(addrlatch == ADDR_PROGDATA) ? progaddr :
74610a87 JW	124	23'b0;
74610a87 JW	125
a8f4468d	126	always @(posedge clk) begin
74610a87 JW	127	case (address)
	128	ADDR_PROGADDRH: if (wr) progaddrh <= data;
	129	ADDR_PROGADDRM: if (wr) progaddrm <= data;
	130	ADDR_PROGADDRL: if (wr) progaddrl <= data;
1eefdc8e	131	ADDR_PROGDATA: if (rd \|\| wr) begin
3db3fc27 JW	132	progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
3db3fc27 JW	133	{progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
1eefdc8e	134	end
6d070aee JW	135	ADDR_MBC: begin
	136	mbc_emul <= data;
	137	rambank <= 0;
	138	rombank <= 1;
	139	end
74610a87	140	endcase
6d070aee JW	141
	142	if (mbc_emul[6:0] == 5) begin
	143	if ((address[15:12] == 4'h2) && wr)
	144	rombank <= {rombank[8], data};
	145	else if ((address[15:12] == 4'h3) && wr)
	146	rombank <= {data[0], rombank[7:0]};
	147	else if ((address[15:12] == 4'h4) && wr)
	148	rambank <= data[3:0];
	149	end
	150
a8f4468d JW	151	rdlatch <= rd;
	152	wrlatch <= wr;
	153	addrlatch <= address;
	154	datalatch <= data;
	155	end
74610a87	156
a8f4468d JW	157	assign data = (rdlatch && decode) ?
	158	(addrlatch == ADDR_PROGADDRH) ? progaddrh :
	159	(addrlatch == ADDR_PROGADDRM) ? progaddrm :
	160	(addrlatch == ADDR_PROGADDRL) ? progaddrl :
74610a87 JW	161	cr_DQ
	162	: 8'bzzzzzzzz;
	163	endmodule
	164
a85b19a7 JW	165	module InternalRAM(
	166	input [15:0] address,
	167	inout [7:0] data,
	168	input clk,
	169	input wr, rd);
	170
fe3dc890	171	// synthesis attribute ram_style of ram is block
616eebe0	172	reg [7:0] ram [8191:0];
a85b19a7	173
74610a87	174	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7	175	reg [7:0] odata;
a8f4468d JW	176	reg rdlatch = 0;
a8f4468d JW	177	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	178
68ce013e	179	always @(posedge clk)
a85b19a7	180	begin
a8f4468d	181	rdlatch <= rd && decode;
74610a87 JW	182	if (decode) // This has to go this way. The only way XST knows how to do
74610a87 JW	183	begin // block ram is chip select, write enable, and always
95143d64	184	if (wr) // reading. "else if rd" does not cut it ...
616eebe0 JW	185	ram[address[12:0]] <= data;
616eebe0 JW	186	odata <= ram[address[12:0]];
c87db60a	187	end
a85b19a7 JW	188	end
	189	endmodule
	190
	191	module Switches(
	192	input [15:0] address,
	193	inout [7:0] data,
	194	input clk,
	195	input wr, rd,
	196	input [7:0] switches,
9c834ff2	197	output reg [7:0] ledout = 0);
a85b19a7 JW	198
	199	wire decode = address == 16'hFF51;
	200	reg [7:0] odata;
a8f4468d JW	201	reg rdlatch = 0;
a8f4468d JW	202	assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7	203
68ce013e	204	always @(posedge clk)
a85b19a7	205	begin
a8f4468d	206	rdlatch <= rd && decode;
a85b19a7 JW	207	if (decode && rd)
	208	odata <= switches;
	209	else if (decode && wr)
	210	ledout <= data;
	211	end
	212	endmodule
	213
e7fb589a JW	214	`ifdef isim
	215	module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
	216	endmodule
	217	`endif
	218
a85b19a7	219	module CoreTop(
e7fb589a JW	220	`ifdef isim
	221	output reg vgaclk = 0,
	222	output reg clk = 0,
	223	`else
a85b19a7 JW	224	input xtal,
a85b19a7 JW	225	input [7:0] switches,
ff7fd7f2	226	input [3:0] buttons,
a85b19a7 JW	227	output wire [7:0] leds,
a85b19a7 JW	228	output serio,
298e8085	229	input serin,
a85b19a7	230	output wire [3:0] digits,
00573fd5	231	output wire [7:0] seven,
74610a87 JW	232	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
	233	output wire [22:0] cr_A,
	234	inout [15:0] cr_DQ,
e7fb589a	235	`endif
00573fd5 JW	236	output wire hs, vs,
00573fd5 JW	237	output wire [2:0] r, g,
09c1936c JW	238	output wire [1:0] b,
09c1936c JW	239	output wire soundl, soundr);
e7fb589a JW	240
	241	`ifdef isim
	242	always #62 clk <= ~clk;
	243	always #100 vgaclk <= ~vgaclk;
	244
	245	Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7	246
e7fb589a JW	247	wire [7:0] leds;
e7fb589a JW	248	wire serio;
298e8085	249	wire serin = 1;
e7fb589a JW	250	wire [3:0] digits;
	251	wire [7:0] seven;
	252	wire [7:0] switches = 8'b0;
	253	wire [3:0] buttons = 4'b0;
	254	`else
fe3dc890 JW	255	wire xtalb, clk, vgaclk;
	256	IBUFG iclkbuf(.O(xtalb), .I(xtal));
	257	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
	258	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
e7fb589a JW	259	`endif
e7fb589a JW	260
91c74a3f JW	261	wire [15:0] addr [1:0];
	262	wire [7:0] data [1:0];
	263	wire wr [1:0], rd [1:0];
f8db6448	264
00573fd5	265	wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448	266	wire [7:0] jaddr;
6c46357c	267	wire [1:0] state;
d1b40456	268	wire ack;
179b4347	269
a85b19a7	270	GBZ80Core core(
179b4347	271	.clk(clk),
91c74a3f JW	272	.bus0address(addr[0]),
	273	.bus0data(data[0]),
	274	.bus0wr(wr[0]),
	275	.bus0rd(rd[0]),
	276	.bus1address(addr[1]),
	277	.bus1data(data[1]),
	278	.bus1wr(wr[1]),
	279	.bus1rd(rd[1]),
f8db6448	280	.irq(irq),
d1b40456	281	.irqack(ack),
6c46357c JW	282	.jaddr(jaddr),
6c46357c JW	283	.state(state));
a85b19a7	284
91c74a3f JW	285	BootstrapROM brom(
	286	.address(addr[1]),
	287	.data(data[1]),
	288	.clk(clk),
	289	.wr(wr[1]),
	290	.rd(rd[1]));
	291
74610a87	292	`ifdef isim
6d070aee	293	SimROM rom(
91c74a3f JW	294	.address(addr[0]),
91c74a3f JW	295	.data(data[0]),
a85b19a7	296	.clk(clk),
91c74a3f JW	297	.wr(wr[0]),
91c74a3f JW	298	.rd(rd[0]));
74610a87 JW	299	`else
	300	CellularRAM cellram(
	301	.address(addr[0]),
	302	.data(data[0]),
	303	.clk(clk),
	304	.wr(wr[0]),
7c1b9e8e	305	.rd(rd[0]),
74610a87 JW	306	.cr_nADV(cr_nADV),
	307	.cr_nCE(cr_nCE),
	308	.cr_nOE(cr_nOE),
7c1b9e8e	309	.cr_nWE(cr_nWE),
74610a87 JW	310	.cr_CRE(cr_CRE),
	311	.cr_nLB(cr_nLB),
	312	.cr_nUB(cr_nUB),
	313	.cr_CLK(cr_CLK),
	314	.cr_A(cr_A),
	315	.cr_DQ(cr_DQ));
	316	`endif
a85b19a7	317
fe3dc890 JW	318	wire lcdhs, lcdvs, lcdclk;
	319	wire [2:0] lcdr, lcdg;
	320	wire [1:0] lcdb;
	321
537e1f83	322	LCDC lcdc(
537e1f83	323	.clk(clk),
91c74a3f JW	324	.addr(addr[0]),
	325	.data(data[0]),
	326	.wr(wr[0]),
	327	.rd(rd[0]),
00573fd5 JW	328	.lcdcirq(lcdcirq),
00573fd5 JW	329	.vblankirq(vblankirq),
fe3dc890 JW	330	.lcdclk(lcdclk),
	331	.lcdhs(lcdhs),
	332	.lcdvs(lcdvs),
	333	.lcdr(lcdr),
	334	.lcdg(lcdg),
	335	.lcdb(lcdb));
	336
	337	Framebuffer fb(
	338	.lcdclk(lcdclk),
	339	.lcdhs(lcdhs),
	340	.lcdvs(lcdvs),
	341	.lcdr(lcdr),
	342	.lcdg(lcdg),
	343	.lcdb(lcdb),
	344	.vgaclk(vgaclk),
00573fd5 JW	345	.vgahs(hs),
	346	.vgavs(vs),
	347	.vgar(r),
	348	.vgag(g),
	349	.vgab(b));
6d070aee JW	350
	351	Switches sw(
	352	.clk(clk),
	353	.address(addr[0]),
	354	.data(data[0]),
	355	.wr(wr[0]),
	356	.rd(rd[0]),
	357	.ledout(leds),
	358	.switches(switches)
	359	);
	360
a85b19a7	361	AddrMon amon(
eb0f2fe1	362	.clk(clk),
91c74a3f	363	.addr(addr[0]),
eb0f2fe1 JW	364	.digit(digits),
eb0f2fe1 JW	365	.out(seven),
6c46357c JW	366	.freeze(buttons[0]),
6c46357c JW	367	.periods(
179b4347 JW	368	(state == 2'b00) ? 4'b0010 :
	369	(state == 2'b01) ? 4'b0001 :
	370	(state == 2'b10) ? 4'b1000 :
	371	4'b0100) );
a85b19a7	372
06ad3a30	373	UART nouart ( /* no u */
91c74a3f JW	374	.clk(clk),
	375	.addr(addr[0]),
	376	.data(data[0]),
	377	.wr(wr[0]),
	378	.rd(rd[0]),
298e8085 JW	379	.serial(serio),
298e8085 JW	380	.serialrx(serin)
eb0f2fe1	381	);
9aa931d1	382
eb0f2fe1	383	InternalRAM ram(
9aa931d1	384	.clk(clk),
91c74a3f JW	385	.address(addr[0]),
	386	.data(data[0]),
	387	.wr(wr[0]),
	388	.rd(rd[0])
eb0f2fe1	389	);
6bd4619b JW	390
6bd4619b JW	391	MiniRAM mram(
6bd4619b	392	.clk(clk),
91c74a3f JW	393	.address(addr[1]),
	394	.data(data[1]),
	395	.wr(wr[1]),
	396	.rd(rd[1])
6bd4619b	397	);
06ad3a30	398
06ad3a30 JW	399	Timer tmr(
06ad3a30 JW	400	.clk(clk),
91c74a3f JW	401	.addr(addr[0]),
	402	.data(data[0]),
	403	.wr(wr[0]),
	404	.rd(rd[0]),
eb0f2fe1 JW	405	.irq(tmrirq)
eb0f2fe1 JW	406	);
06ad3a30 JW	407
	408	Interrupt intr(
	409	.clk(clk),
91c74a3f JW	410	.addr(addr[0]),
	411	.data(data[0]),
	412	.wr(wr[0]),
	413	.rd(rd[0]),
00573fd5	414	.vblank(vblankirq),
537e1f83	415	.lcdc(lcdcirq),
06ad3a30	416	.tovf(tmrirq),
e7fb589a JW	417	.serial(1'b0),
e7fb589a JW	418	.buttons(1'b0),
06ad3a30	419	.master(irq),
d1b40456	420	.ack(ack),
06ad3a30	421	.jaddr(jaddr));
09c1936c JW	422
	423	Soundcore sound(
	424	.core_clk(clk),
91c74a3f JW	425	.addr(addr[0]),
	426	.data(data[0]),
	427	.rd(rd[0]),
	428	.wr(wr[0]),
09c1936c JW	429	.snd_data_l(soundl),
09c1936c JW	430	.snd_data_r(soundr));
a85b19a7	431	endmodule