Add a first cut at strataflash support
[fpgaboy.git] / System.v
CommitLineData
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1
2`timescale 1ns / 1ps
6d070aee 3module SimROM(
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4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
a8f4468d 9 reg rdlatch = 0;
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10 reg [7:0] odata;
11
6d070aee 12 reg [7:0] rom [32767:0];
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13 initial $readmemh("rom.hex", rom);
14
15 wire decode = address[15:13] == 0;
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16 always @(posedge clk) begin
17 rdlatch <= rd && decode;
2854e399 18 odata <= rom[address[10:0]];
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19 end
20 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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21endmodule
22
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23module BootstrapROM(
24 input [15:0] address,
25 inout [7:0] data,
26 input clk,
27 input wr, rd);
28
a8f4468d 29 reg rdlatch = 0;
e29171aa 30 reg [7:0] addrlatch = 0;
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31 reg romno = 0, romnotmp = 0;
32 reg [7:0] brom0 [255:0];
33 reg [7:0] brom1 [255:0];
34
35 initial $readmemh("fpgaboot.hex", brom0);
36 initial $readmemh("gbboot.hex", brom1);
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37
38`ifdef isim
39 initial romno <= 1;
40`endif
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41
42 wire decode = address[15:8] == 0;
49c326da 43 wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
e29171aa 44 always @(posedge clk) begin
a8f4468d 45 rdlatch <= rd && decode;
e29171aa 46 addrlatch <= address[7:0];
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47 if (wr && decode) romnotmp <= data[0];
48 if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
e29171aa 49 end
a8f4468d 50 assign data = rdlatch ? odata : 8'bzzzzzzzz;
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51endmodule
52
53module MiniRAM(
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54 input [15:0] address,
55 inout [7:0] data,
56 input clk,
57 input wr, rd);
58
59 reg [7:0] ram [127:0];
60
61 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
a8f4468d 62 reg rdlatch = 0;
6bd4619b 63 reg [7:0] odata;
a8f4468d 64 assign data = rdlatch ? odata : 8'bzzzzzzzz;
6bd4619b 65
68ce013e 66 always @(posedge clk)
6bd4619b 67 begin
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68 rdlatch <= rd && decode;
69 if (decode) // This has to go this way. The only way XST knows how to do
70 begin // block ram is chip select, write enable, and always
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71 if (wr) // reading. "else if rd" does not cut it ...
72 ram[address[6:0]] <= data;
73 odata <= ram[address[6:0]];
74 end
75 end
c279b666 76endmodule
6bd4619b 77
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78module CellularRAM(
79 input clk,
80 input [15:0] address,
81 inout [7:0] data,
82 input wr, rd,
83 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
8e36c4ed 84 output wire st_nCE, st_nRST,
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85 output wire [22:0] cr_A,
86 inout [15:0] cr_DQ);
87
88 parameter ADDR_PROGADDRH = 16'hFF60;
89 parameter ADDR_PROGADDRM = 16'hFF61;
90 parameter ADDR_PROGADDRL = 16'hFF62;
91 parameter ADDR_PROGDATA = 16'hFF63;
8e36c4ed 92 parameter ADDR_PROGFLASH = 16'hFF65;
6d070aee 93 parameter ADDR_MBC = 16'hFF64;
74610a87 94
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95 reg rdlatch = 0, wrlatch = 0;
96 reg [15:0] addrlatch = 0;
97 reg [7:0] datalatch = 0;
98
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99 reg [7:0] progaddrh, progaddrm, progaddrl;
100
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101 reg [22:0] progaddr;
102
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103 reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash
104 // low 7 bits are the MBC that we are emulating
105
74610a87 106 assign cr_nADV = 0; /* Addresses are always valid! :D */
8e36c4ed 107 assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
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108 assign cr_nLB = 0; /* Lower byte is enabled */
109 assign cr_nUB = 0; /* Upper byte is enabled */
110 assign cr_CRE = 0; /* Data writes, not config */
111 assign cr_CLK = 0; /* Clock? I think not! */
112
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113 assign st_nRST = 1; /* Keep the strataflash out of reset. */
114 assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
115
116 wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
74610a87 117
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118 reg [3:0] rambank = 0;
119 reg [8:0] rombank = 1;
120
a8f4468d 121 assign cr_nOE = decode ? ~rdlatch : 1;
8e36c4ed 122 assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
74610a87 123
a8f4468d 124 assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
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125 assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
126 (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
127 (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
8e36c4ed 128 ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
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129 23'b0;
130
a8f4468d 131 always @(posedge clk) begin
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132 case (address)
133 ADDR_PROGADDRH: if (wr) progaddrh <= data;
134 ADDR_PROGADDRM: if (wr) progaddrm <= data;
135 ADDR_PROGADDRL: if (wr) progaddrl <= data;
1eefdc8e 136 ADDR_PROGDATA: if (rd || wr) begin
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137 progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
138 {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
1eefdc8e 139 end
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140 ADDR_MBC: begin
141 mbc_emul <= data;
142 rambank <= 0;
143 rombank <= 1;
144 end
74610a87 145 endcase
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146
147 if (mbc_emul[6:0] == 5) begin
148 if ((address[15:12] == 4'h2) && wr)
149 rombank <= {rombank[8], data};
150 else if ((address[15:12] == 4'h3) && wr)
151 rombank <= {data[0], rombank[7:0]};
152 else if ((address[15:12] == 4'h4) && wr)
153 rambank <= data[3:0];
154 end
155
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156 rdlatch <= rd;
157 wrlatch <= wr;
158 addrlatch <= address;
159 datalatch <= data;
160 end
74610a87 161
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162 assign data = (rdlatch && decode) ?
163 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
164 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
165 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
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166 cr_DQ
167 : 8'bzzzzzzzz;
168endmodule
169
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170module InternalRAM(
171 input [15:0] address,
172 inout [7:0] data,
173 input clk,
174 input wr, rd);
175
fe3dc890 176 // synthesis attribute ram_style of ram is block
616eebe0 177 reg [7:0] ram [8191:0];
a85b19a7 178
74610a87 179 wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */
a85b19a7 180 reg [7:0] odata;
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181 reg rdlatch = 0;
182 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 183
68ce013e 184 always @(posedge clk)
a85b19a7 185 begin
a8f4468d 186 rdlatch <= rd && decode;
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187 if (decode) // This has to go this way. The only way XST knows how to do
188 begin // block ram is chip select, write enable, and always
95143d64 189 if (wr) // reading. "else if rd" does not cut it ...
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190 ram[address[12:0]] <= data;
191 odata <= ram[address[12:0]];
c87db60a 192 end
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193 end
194endmodule
195
196module Switches(
197 input [15:0] address,
198 inout [7:0] data,
199 input clk,
200 input wr, rd,
201 input [7:0] switches,
9c834ff2 202 output reg [7:0] ledout = 0);
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203
204 wire decode = address == 16'hFF51;
205 reg [7:0] odata;
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206 reg rdlatch = 0;
207 assign data = rdlatch ? odata : 8'bzzzzzzzz;
a85b19a7 208
68ce013e 209 always @(posedge clk)
a85b19a7 210 begin
a8f4468d 211 rdlatch <= rd && decode;
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212 if (decode && rd)
213 odata <= switches;
214 else if (decode && wr)
215 ledout <= data;
216 end
217endmodule
218
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219`ifdef isim
220module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
221endmodule
222`endif
223
a85b19a7 224module CoreTop(
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225`ifdef isim
226 output reg vgaclk = 0,
227 output reg clk = 0,
228`else
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229 input xtal,
230 input [7:0] switches,
ff7fd7f2 231 input [3:0] buttons,
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232 output wire [7:0] leds,
233 output serio,
298e8085 234 input serin,
a85b19a7 235 output wire [3:0] digits,
00573fd5 236 output wire [7:0] seven,
8e36c4ed 237 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
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238 output wire [22:0] cr_A,
239 inout [15:0] cr_DQ,
bc75fc67 240 input ps2c, ps2d,
e7fb589a 241`endif
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242 output wire hs, vs,
243 output wire [2:0] r, g,
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244 output wire [1:0] b,
245 output wire soundl, soundr);
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246
247`ifdef isim
248 always #62 clk <= ~clk;
249 always #100 vgaclk <= ~vgaclk;
250
251 Dumpable dump(r,g,b,hs,vs,vgaclk);
a85b19a7 252
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253 wire [7:0] leds;
254 wire serio;
298e8085 255 wire serin = 1;
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256 wire [3:0] digits;
257 wire [7:0] seven;
258 wire [7:0] switches = 8'b0;
259 wire [3:0] buttons = 4'b0;
260`else
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261 wire xtalb, clk, vgaclk;
262 IBUFG iclkbuf(.O(xtalb), .I(xtal));
263 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
264 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
bc75fc67 265 wire [7:0] ps2buttons;
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266`endif
267
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268 wire [15:0] addr [1:0];
269 wire [7:0] data [1:0];
270 wire wr [1:0], rd [1:0];
f8db6448 271
a6b499da 272 wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
f8db6448 273 wire [7:0] jaddr;
6c46357c 274 wire [1:0] state;
d1b40456 275 wire ack;
179b4347 276
a85b19a7 277 GBZ80Core core(
179b4347 278 .clk(clk),
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279 .bus0address(addr[0]),
280 .bus0data(data[0]),
281 .bus0wr(wr[0]),
282 .bus0rd(rd[0]),
283 .bus1address(addr[1]),
284 .bus1data(data[1]),
285 .bus1wr(wr[1]),
286 .bus1rd(rd[1]),
f8db6448 287 .irq(irq),
d1b40456 288 .irqack(ack),
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289 .jaddr(jaddr),
290 .state(state));
a85b19a7 291
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292 BootstrapROM brom(
293 .address(addr[1]),
294 .data(data[1]),
295 .clk(clk),
296 .wr(wr[1]),
297 .rd(rd[1]));
298
74610a87 299`ifdef isim
6d070aee 300 SimROM rom(
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301 .address(addr[0]),
302 .data(data[0]),
a85b19a7 303 .clk(clk),
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304 .wr(wr[0]),
305 .rd(rd[0]));
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306`else
307 CellularRAM cellram(
308 .address(addr[0]),
309 .data(data[0]),
310 .clk(clk),
311 .wr(wr[0]),
7c1b9e8e 312 .rd(rd[0]),
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313 .cr_nADV(cr_nADV),
314 .cr_nCE(cr_nCE),
315 .cr_nOE(cr_nOE),
7c1b9e8e 316 .cr_nWE(cr_nWE),
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317 .cr_CRE(cr_CRE),
318 .cr_nLB(cr_nLB),
319 .cr_nUB(cr_nUB),
320 .cr_CLK(cr_CLK),
321 .cr_A(cr_A),
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322 .cr_DQ(cr_DQ),
323 .st_nCE(st_nCE),
324 .st_nRST(st_nRST));
74610a87 325`endif
a85b19a7 326
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327 wire lcdhs, lcdvs, lcdclk;
328 wire [2:0] lcdr, lcdg;
329 wire [1:0] lcdb;
330
537e1f83 331 LCDC lcdc(
537e1f83 332 .clk(clk),
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333 .addr(addr[0]),
334 .data(data[0]),
335 .wr(wr[0]),
336 .rd(rd[0]),
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337 .lcdcirq(lcdcirq),
338 .vblankirq(vblankirq),
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339 .lcdclk(lcdclk),
340 .lcdhs(lcdhs),
341 .lcdvs(lcdvs),
342 .lcdr(lcdr),
343 .lcdg(lcdg),
344 .lcdb(lcdb));
345
346 Framebuffer fb(
347 .lcdclk(lcdclk),
348 .lcdhs(lcdhs),
349 .lcdvs(lcdvs),
350 .lcdr(lcdr),
351 .lcdg(lcdg),
352 .lcdb(lcdb),
353 .vgaclk(vgaclk),
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354 .vgahs(hs),
355 .vgavs(vs),
356 .vgar(r),
357 .vgag(g),
358 .vgab(b));
6d070aee 359
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360 wire [7:0] sleds;
361`ifdef isim
362 assign leds = sleds;
363`else
364 assign leds = sleds | ps2buttons;
365`endif
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366 Switches sw(
367 .clk(clk),
368 .address(addr[0]),
369 .data(data[0]),
370 .wr(wr[0]),
371 .rd(rd[0]),
bc75fc67 372 .ledout(sleds),
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373 .switches(switches)
374 );
a6b499da 375
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376`ifdef isim
377`else
378 PS2Button ps2(
b057a5d6 379 .clk(clk),
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380 .inclk(ps2c),
381 .indata(ps2d),
382 .buttons(ps2buttons)
383 );
384`endif
385
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386 Buttons ass(
387 .core_clk(clk),
388 .addr(addr[0]),
389 .data(data[0]),
390 .wr(wr[0]),
391 .rd(rd[0]),
392 .int(btnirq),
bc75fc67 393 `ifdef isim
a6b499da 394 .buttons(switches)
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395 `else
396 .buttons(ps2buttons)
397 `endif
a6b499da 398 );
6d070aee 399
a85b19a7 400 AddrMon amon(
eb0f2fe1 401 .clk(clk),
91c74a3f 402 .addr(addr[0]),
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403 .digit(digits),
404 .out(seven),
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405 .freeze(buttons[0]),
406 .periods(
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407 (state == 2'b00) ? 4'b0010 :
408 (state == 2'b01) ? 4'b0001 :
409 (state == 2'b10) ? 4'b1000 :
410 4'b0100) );
a85b19a7 411
06ad3a30 412 UART nouart ( /* no u */
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413 .clk(clk),
414 .addr(addr[0]),
415 .data(data[0]),
416 .wr(wr[0]),
417 .rd(rd[0]),
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418 .serial(serio),
419 .serialrx(serin)
eb0f2fe1 420 );
9aa931d1 421
eb0f2fe1 422 InternalRAM ram(
9aa931d1 423 .clk(clk),
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424 .address(addr[0]),
425 .data(data[0]),
426 .wr(wr[0]),
427 .rd(rd[0])
eb0f2fe1 428 );
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429
430 MiniRAM mram(
6bd4619b 431 .clk(clk),
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432 .address(addr[1]),
433 .data(data[1]),
434 .wr(wr[1]),
435 .rd(rd[1])
6bd4619b 436 );
06ad3a30 437
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438 Timer tmr(
439 .clk(clk),
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440 .addr(addr[0]),
441 .data(data[0]),
442 .wr(wr[0]),
443 .rd(rd[0]),
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444 .irq(tmrirq)
445 );
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446
447 Interrupt intr(
448 .clk(clk),
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449 .addr(addr[0]),
450 .data(data[0]),
451 .wr(wr[0]),
452 .rd(rd[0]),
00573fd5 453 .vblank(vblankirq),
537e1f83 454 .lcdc(lcdcirq),
06ad3a30 455 .tovf(tmrirq),
e7fb589a 456 .serial(1'b0),
a6b499da 457 .buttons(btnirq),
06ad3a30 458 .master(irq),
d1b40456 459 .ack(ack),
06ad3a30 460 .jaddr(jaddr));
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461
462 Soundcore sound(
463 .core_clk(clk),
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464 .addr(addr[0]),
465 .data(data[0]),
466 .rd(rd[0]),
467 .wr(wr[0]),
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468 .snd_data_l(soundl),
469 .snd_data_r(soundr));
a85b19a7 470endmodule
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