Joshua Wise's Git repositories - firearm.git/history

]> Joshua Wise's Git repositories - firearm.git/history - Execute.v

git.joshuawise.com / firearm.git / history

2010-03-11	Joshua Wise	Execute: Pass 1 repiping finished.	blob \| commitdiff \| raw
2010-03-10	Joshua Wise	Global: More re-piping, and a bugfix for a bug recently...	blob \| commitdiff \| raw \| diff to current
2009-01-24	Joshua Wise	Execute: Split things out into their own always blocks...	blob \| commitdiff \| raw \| diff to current
2009-01-23	Joshua Wise	Execute: Fix carry flag on subtraction operations.	blob \| commitdiff \| raw \| diff to current
2009-01-22	Joshua Wise	Execute: Branches allow somebody else to take precedenc...	blob \| commitdiff \| raw \| diff to current
2009-01-22	Joshua Wise	system, Writeback, Memory, Execute: Only update the...	blob \| commitdiff \| raw \| diff to current
2009-01-15	Joshua Wise	Execute: fix rdiff	blob \| commitdiff \| raw \| diff to current
2009-01-14	Joshua Wise	Execute: Fix outbubble on multiplier so that it remembe...	blob \| commitdiff \| raw \| diff to current
2009-01-14	Joshua Wise	Execute: Add delayed flush logic.	blob \| commitdiff \| raw \| diff to current
2009-01-10	Joshua Wise	Execute: Fix jumps while flush asserted. Set lr correc...	blob \| commitdiff \| raw \| diff to current
2009-01-10	Christopher Lu	Merge branch 'master' of nyus.joshuawise.com:/git/firearm	blob \| commitdiff \| raw \| diff to current
2009-01-09	Joshua Wise	Merge nyus:/storage/git/firearm	blob \| commitdiff \| raw \| diff to current
2009-01-09	Joshua Wise	Hit all with the integrate.	blob \| commitdiff \| raw \| diff to current
2009-01-06	Christopher Lu	merge memory	blob \| commitdiff \| raw \| diff to current
2009-01-06	Joshua Wise	Wire in Memory. Fix small bug in Memory involving...	blob \| commitdiff \| raw \| diff to current
2009-01-06	Joshua Wise	Execute.v: Add outpc and outinsn. System.v: Add and...	blob \| commitdiff \| raw \| diff to current
2009-01-05	Joshua Wise	Ok, it work.	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	execute: do stuff only if bubble, still incorrect	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	added branch support, maybe	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	Merge branch 'master' of nyus.joshuawise.com:/git/firearm	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	really fix execute	blob \| commitdiff \| raw \| diff to current
2009-01-05	Joshua Wise	Merge nyus:/storage/git/firearm	blob \| commitdiff \| raw \| diff to current
2009-01-05	Joshua Wise	Add SPSR logic to Execute.	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	branch added	blob \| commitdiff \| raw \| diff to current
2009-01-05	Christopher Lu	fixed v flag	blob \| commitdiff \| raw \| diff to current
2008-12-31	Joshua Wise	Execute.v: Execute multiplication happily	blob \| commitdiff \| raw \| diff to current
2008-12-31	Joshua Wise	Execute.v: Wire up the ALU.	blob \| commitdiff \| raw \| diff to current
2008-12-31	Joshua Wise	Add skeleton to Execute.v	blob \| commitdiff \| raw \| diff to current
2008-12-30	Joshua Wise	Add wires for ALU.	blob \| commitdiff \| raw \| diff to current
2008-12-29	Christopher Lu	Execute: most of an ALU, ARM_Constants: RBC -> RSC	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	Merge nyus:/storage/git/firearm	blob \| commitdiff \| raw \| diff to current
2008-12-28	Christopher Lu	Merge branch 'master' of nyus.joshuawise.com:/git/firearm	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	do some first pass Execute wiring	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	Merge nyus:/storage/git/firearm	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	holy shit my multiplier compiled the first time o__o	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	elanus	blob \| commitdiff \| raw \| diff to current
2008-12-28	Joshua Wise	add execute skeleton	blob \| commitdiff \| raw \| diff to current

FireARM pipelined ARM-like CPU implementation in Verilog

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