Execute.v

   1 module Execute(
   2         input clk,
   3         input Nrst,     /* XXX not used yet */
   4
   5         input stall,
   6         input flush,
   7
   8         input inbubble,
   9         input [31:0] pc,
  10         input [31:0] insn,
  11         input [31:0] cpsr,
  12         input [31:0] op0,
  13         input [31:0] op1,
  14         input [31:0] op2,
  15         input carry,
  16
  17         output reg outstall = 0,
  18         output reg outbubble = 1,
  19         output reg [31:0] outcpsr = 0,
  20         output reg write_reg = 1'bx,
  21         output reg [3:0] write_num = 4'bxxxx,
  22         output reg [31:0] write_data = 32'hxxxxxxxx,
  23         output reg [31:0] outpc,
  24         output reg outflush
  25         );
  26
  27         reg mult_start;
  28         reg [31:0] mult_acc0, mult_in0, mult_in1;
  29         wire mult_done;
  30         wire [31:0] mult_result;
  31
  32         reg [31:0] alu_in0, alu_in1;
  33         reg [3:0] alu_op;
  34         reg alu_setflags;
  35         wire [31:0] alu_result, alu_outcpsr;
  36         wire alu_setres;
  37
  38         reg next_outbubble;
  39         reg [31:0] next_outcpsr;
  40         reg next_write_reg;
  41         reg [3:0] next_write_num;
  42         reg [31:0] next_write_data;
  43
  44         Multiplier multiplier(
  45                 .clk(clk), .Nrst(Nrst),
  46                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
  47                 .in1(mult_in1), .done(mult_done), .result(mult_result));
  48
  49         ALU alu(
  50                 .clk(clk), .Nrst(Nrst),
  51                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
  52                 .setflags(alu_setflags), .shifter_carry(carry),
  53                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
  54
  55         always @(posedge clk)
  56         begin
  57                 if (!stall)
  58                 begin
  59                         outbubble <= next_outbubble;
  60                         outcpsr <= next_outcpsr;
  61                         write_reg <= next_write_reg;
  62                         write_num <= next_write_num;
  63                         write_data <= next_write_data;
  64                 end
  65         end
  66
  67         reg prevstall = 0;
  68         always @(posedge clk)
  69                 prevstall <= outstall;
  70
  71         always @(*)
  72         begin
  73                 outstall = stall;
  74                 next_outbubble = inbubble;
  75                 next_outcpsr = cpsr;
  76                 next_write_reg = 0;
  77                 next_write_num = 4'hx;
  78                 next_write_data = 32'hxxxxxxxx;
  79
  80                 mult_start = 0;
  81                 mult_acc0 = 32'hxxxxxxxx;
  82                 mult_in0 = 32'hxxxxxxxx;
  83                 mult_in1 = 32'hxxxxxxxx;
  84
  85                 alu_in0 = 32'hxxxxxxxx;
  86                 alu_in1 = 32'hxxxxxxxx;
  87                 alu_op = 4'hx;  /* hax! */
  88                 alu_setflags = 1'bx;
  89
  90                 casez (insn)
  91                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  92                 begin
  93                         if (!prevstall && !inbubble)
  94                         begin
  95                                 mult_start = 1;
  96                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
  97                                 mult_in0 = op1 /* Rm */;
  98                                 mult_in1 = op2 /* Rs */;
  99                                 $display("New MUL instruction");
 100                         end
 101                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
 102                         next_outbubble = inbubble | !mult_done | !prevstall;
 103                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 104                         next_write_reg = 1;
 105                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 106                         next_write_data = mult_result;
 107                 end
 108 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
 109                 `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
 110                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 111                 `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 112                 `DECODE_ALU_SWP,        /* Atomic swap */
 113                 `DECODE_ALU_BX,         /* Branch */
 114                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
 115                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 116                 begin end
 117                 `DECODE_ALU:            /* ALU */
 118                 begin
 119                         alu_in0 = op0;
 120                         alu_in1 = op1;
 121                         alu_op = insn[24:21];
 122                         alu_setflags = insn[20] /* I */;
 123
 124                         if (alu_setres) begin
 125                                 next_write_reg = 1;
 126                                 next_write_num = insn[15:12] /* Rd */;
 127                                 next_write_data = alu_result;
 128                         end
 129
 130                         next_outcpsr = alu_outcpsr;
 131                 end
 132                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
 133                 `DECODE_LDRSTR,         /* Single data transfer */
 134                 `DECODE_LDMSTM:         /* Block data transfer */
 135                 begin end
 136                 `DECODE_BRANCH:
 137                 begin
 138                         outpc = pc + op0;
 139                         if(insn[24]) begin
 140                                 next_write_reg = 1;
 141                                 next_write_num = 4'hE; /* link register */
 142                                 next_write_data = pc + 32'h4;
 143                         end
 144                 end                     /* Branch */
 145                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
 146                 `DECODE_CDP,            /* Coprocessor data op */
 147                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
 148                 `DECODE_SWI:            /* SWI */
 149                 begin end
 150                 default:                /* X everything else out */
 151                 begin end
 152                 endcase
 153         end
 154 endmodule
 155
 156 module Multiplier(
 157         input clk,
 158         input Nrst,     /* XXX not used yet */
 159
 160         input start,
 161         input [31:0] acc0,
 162         input [31:0] in0,
 163         input [31:0] in1,
 164
 165         output reg done = 0,
 166         output reg [31:0] result);
 167
 168         reg [31:0] bitfield;
 169         reg [31:0] multiplicand;
 170         reg [31:0] acc;
 171
 172         always @(posedge clk)
 173         begin
 174                 if (start) begin
 175                         bitfield <= in0;
 176                         multiplicand <= in1;
 177                         acc <= acc0;
 178                         done <= 0;
 179                 end else begin
 180                         bitfield <= {2'b00, bitfield[31:2]};
 181                         multiplicand <= {multiplicand[29:0], 2'b00};
 182                         acc <= acc +
 183                                 (bitfield[0] ? multiplicand : 0) +
 184                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
 185                         if (bitfield == 0) begin
 186                                 result <= acc;
 187                                 done <= 1;
 188                         end
 189                 end
 190         end
 191 endmodule
 192
 193 module ALU(
 194         input clk,
 195         input Nrst,     /* XXX not used yet */
 196
 197         input [31:0] in0,
 198         input [31:0] in1,
 199         input [31:0] cpsr,
 200         input [3:0] op,
 201         input setflags,
 202         input shifter_carry,
 203
 204         output reg [31:0] result,
 205         output reg [31:0] cpsr_out,
 206         output reg setres
 207 );
 208         wire [31:0] res;
 209         wire flag_n, flag_z, flag_c, flag_v, setres;
 210         wire [32:0] sum, diff, rdiff;
 211         wire sum_v, diff_v, rdiff_v;
 212
 213         assign sum = {1'b0, in0} + {1'b0, in1};
 214         assign diff = {1'b0, in0} - {1'b0, in1};
 215         assign rdiff = {1'b0, in1} + {1'b0, in0};
 216         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 217         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 218         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 219
 220         always @(*) begin
 221                 res = 32'hxxxxxxxx;
 222                 setres = 1'bx;
 223                 flag_c = cpsr[`CPSR_C];
 224                 flag_v = cpsr[`CPSR_V];
 225                 case(op)
 226                 `ALU_AND: begin
 227                         result = in0 & in1;
 228                         flag_c = shifter_carry;
 229                         setres = 1'b1;
 230                 end
 231                 `ALU_EOR: begin
 232                         result = in0 ^ in1;
 233                         flag_c = shifter_carry;
 234                         setres = 1'b1;
 235                 end
 236                 `ALU_SUB: begin
 237                         {flag_c, result} = diff;
 238                         flag_v = diff_v;
 239                         setres = 1'b1;
 240                 end
 241                 `ALU_RSB: begin
 242                         {flag_c, result} = rdiff;
 243                         flag_v = rdiff_v;
 244                         setres = 1'b1;
 245                 end
 246                 `ALU_ADD: begin
 247                         {flag_c, result} = sum;
 248                         flag_v = sum_v;
 249                         setres = 1'b1;
 250                 end
 251                 `ALU_ADC: begin
 252                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
 253                         flag_v = sum_v | (~sum[31] & result[31]);
 254                         setres = 1'b1;
 255                 end
 256                 `ALU_SBC: begin
 257                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
 258                         flag_v = diff_v | (diff[31] & ~result[31]);
 259                         setres = 1'b1;
 260                 end
 261                 `ALU_RSC: begin
 262                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
 263                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
 264                         setres = 1'b1;
 265                 end
 266                 `ALU_TST: begin
 267                         result = in0 & in1;
 268                         flag_c = shifter_carry;
 269                         setres = 1'b0;
 270                 end
 271                 `ALU_TEQ: begin
 272                         result = in0 ^ in1;
 273                         flag_c = shifter_carry;
 274                         setres = 1'b0;
 275                 end
 276                 `ALU_CMP: begin
 277                         {flag_c, result} = diff;
 278                         flag_v = diff_v;
 279                         setres = 1'b0;
 280                 end
 281                 `ALU_CMN: begin
 282                         {flag_c, result} = sum;
 283                         flag_v = sum_v;
 284                         setres = 1'b0;
 285                 end
 286                 `ALU_ORR: begin
 287                         result = in0 | in1;
 288                         flag_c = shifter_carry;
 289                         setres = 1'b1;
 290                 end
 291                 `ALU_MOV: begin
 292                         result = in1;
 293                         flag_c = shifter_carry;
 294                         setres = 1'b1;
 295                 end
 296                 `ALU_BIC: begin
 297                         result = in0 & (~in1);
 298                         flag_c = shifter_carry;
 299                         setres = 1'b1;
 300                 end
 301                 `ALU_MVN: begin
 302                         result = ~in1;
 303                         flag_c = shifter_carry;
 304                         setres = 1'b1;
 305                 end
 306                 endcase
 307
 308                 flag_z = (result == 0);
 309                 flag_n = result[31];
 310
 311                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
 312         end
 313 endmodule