fixed v flag
[firearm.git] / Execute.v
1 module Execute(
2         input clk,
3         input Nrst,     /* XXX not used yet */
4         
5         input stall,
6         input flush,
7         
8         input inbubble,
9         input [31:0] pc,
10         input [31:0] insn,
11         input [31:0] cpsr,
12         input [31:0] op0,
13         input [31:0] op1,
14         input [31:0] op2,
15         input carry,
16         
17         output reg outstall = 0,
18         output reg outbubble = 1,
19         output reg [31:0] outcpsr = 0,
20         output reg write_reg = 1'bx,
21         output reg [3:0] write_num = 4'bxxxx,
22         output reg [31:0] write_data = 32'hxxxxxxxx
23         );
24         
25         reg mult_start;
26         reg [31:0] mult_acc0, mult_in0, mult_in1;
27         wire mult_done;
28         wire [31:0] mult_result;
29         
30         reg [31:0] alu_in0, alu_in1;
31         reg [3:0] alu_op;
32         reg alu_setflags;
33         wire [31:0] alu_result, alu_outcpsr;
34         wire alu_setres;
35         
36         reg next_outbubble;
37         reg [31:0] next_outcpsr;
38         reg next_write_reg;
39         reg [3:0] next_write_num;
40         reg [31:0] next_write_data;
41         
42         Multiplier multiplier(
43                 .clk(clk), .Nrst(Nrst),
44                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
45                 .in1(mult_in1), .done(mult_done), .result(mult_result));
46         
47         ALU alu(
48                 .clk(clk), .Nrst(Nrst),
49                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
50                 .setflags(alu_setflags), .shifter_carry(carry),
51                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
52         
53         always @(posedge clk)
54         begin
55                 if (!stall)
56                 begin
57                         outbubble <= next_outbubble;
58                         outcpsr <= next_outcpsr;
59                         write_reg <= next_write_reg;
60                         write_num <= next_write_num;
61                         write_data <= next_write_data;
62                 end
63         end
64
65         reg prevstall = 0;
66         always @(posedge clk)
67                 prevstall <= outstall;
68
69         always @(*)
70         begin
71                 outstall = stall;
72                 next_outbubble = inbubble;
73                 next_outcpsr = cpsr;
74                 next_write_reg = 0;
75                 next_write_num = 4'hx;
76                 next_write_data = 32'hxxxxxxxx;
77         
78                 mult_start = 0;
79                 mult_acc0 = 32'hxxxxxxxx;
80                 mult_in0 = 32'hxxxxxxxx;
81                 mult_in1 = 32'hxxxxxxxx;
82         
83                 alu_in0 = 32'hxxxxxxxx;
84                 alu_in1 = 32'hxxxxxxxx;
85                 alu_op = 4'hx;  /* hax! */
86                 alu_setflags = 1'bx;
87                 
88                 casez (insn)
89                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
90                 begin
91                         if (!prevstall && !inbubble)
92                         begin
93                                 mult_start = 1;
94                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
95                                 mult_in0 = op1 /* Rm */;
96                                 mult_in1 = op2 /* Rs */;
97                                 $display("New MUL instruction");
98                         end
99                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
100                         next_outbubble = inbubble | !mult_done | !prevstall;
101                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
102                         next_write_reg = 1;
103                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
104                         next_write_data = mult_result;
105                 end
106 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
107                 `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
108                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
109                 `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
110                 `DECODE_ALU_SWP,        /* Atomic swap */
111                 `DECODE_ALU_BX,         /* Branch */
112                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
113                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
114                 begin end
115                 `DECODE_ALU:            /* ALU */
116                 begin
117                         alu_in0 = op0;
118                         alu_in1 = op1;
119                         alu_op = insn[24:21];
120                         alu_setflags = insn[20] /* I */;
121                         
122                         if (alu_setres) begin
123                                 next_write_reg = 1;
124                                 next_write_num = insn[15:12] /* Rd */;
125                                 next_write_data = alu_result;
126                         end
127                         
128                         next_outcpsr = alu_outcpsr;
129                 end
130                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
131                 `DECODE_LDRSTR,         /* Single data transfer */
132                 `DECODE_LDMSTM,         /* Block data transfer */
133                 `DECODE_BRANCH,         /* Branch */
134                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
135                 `DECODE_CDP,            /* Coprocessor data op */
136                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
137                 `DECODE_SWI:            /* SWI */
138                 begin end
139                 default:                /* X everything else out */
140                 begin end
141                 endcase
142         end
143 endmodule
144
145 module Multiplier(
146         input clk,
147         input Nrst,     /* XXX not used yet */
148         
149         input start,
150         input [31:0] acc0,
151         input [31:0] in0,
152         input [31:0] in1,
153         
154         output reg done = 0,
155         output reg [31:0] result);
156         
157         reg [31:0] bitfield;
158         reg [31:0] multiplicand;
159         reg [31:0] acc;
160         
161         always @(posedge clk)
162         begin
163                 if (start) begin
164                         bitfield <= in0;
165                         multiplicand <= in1;
166                         acc <= acc0;
167                         done <= 0;
168                 end else begin
169                         bitfield <= {2'b00, bitfield[31:2]};
170                         multiplicand <= {multiplicand[29:0], 2'b00};
171                         acc <= acc +
172                                 (bitfield[0] ? multiplicand : 0) +
173                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
174                         if (bitfield == 0) begin
175                                 result <= acc;
176                                 done <= 1;
177                         end
178                 end
179         end
180 endmodule
181
182 module ALU(
183         input clk,
184         input Nrst,     /* XXX not used yet */
185
186         input [31:0] in0,
187         input [31:0] in1,
188         input [31:0] cpsr,
189         input [3:0] op,
190         input setflags,
191         input shifter_carry,
192
193         output reg [31:0] result,
194         output reg [31:0] cpsr_out,
195         output reg setres
196 );
197         wire [31:0] res;
198         wire flag_n, flag_z, flag_c, flag_v, setres;
199         wire [32:0] sum, diff, rdiff;
200         wire sum_v, diff_v, rdiff_v;
201
202         assign sum = {1'b0, in0} + {1'b0, in1};
203         assign diff = {1'b0, in0} - {1'b0, in1};
204         assign rdiff = {1'b0, in1} + {1'b0, in0};
205         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
206         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
207         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
208
209         always @(*) begin
210                 res = 32'hxxxxxxxx;
211                 setres = 1'bx;
212                 flag_c = cpsr[`CPSR_C];
213                 flag_v = cpsr[`CPSR_V];
214                 case(op)
215                 `ALU_AND: begin
216                         result = in0 & in1;
217                         flag_c = shifter_carry;
218                         setres = 1'b1;
219                 end
220                 `ALU_EOR: begin
221                         result = in0 ^ in1;
222                         flag_c = shifter_carry;
223                         setres = 1'b1;
224                 end
225                 `ALU_SUB: begin
226                         {flag_c, result} = diff;
227                         flag_v = diff_v;
228                         setres = 1'b1;
229                 end
230                 `ALU_RSB: begin
231                         {flag_c, result} = rdiff;
232                         flag_v = rdiff_v;
233                         setres = 1'b1;
234                 end
235                 `ALU_ADD: begin
236                         {flag_c, result} = sum;
237                         flag_v = sum_v;
238                         setres = 1'b1;
239                 end
240                 `ALU_ADC: begin
241                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
242                         flag_v = sum_v | (~sum[31] & result[31]);
243                         setres = 1'b1;
244                 end
245                 `ALU_SBC: begin
246                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
247                         flag_v = diff_v | (diff[31] & ~result[31]);
248                         setres = 1'b1;
249                 end
250                 `ALU_RSC: begin
251                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
252                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
253                         setres = 1'b1;
254                 end
255                 `ALU_TST: begin
256                         result = in0 & in1;
257                         flag_c = shifter_carry;
258                         setres = 1'b0;
259                 end
260                 `ALU_TEQ: begin
261                         result = in0 ^ in1;
262                         flag_c = shifter_carry;
263                         setres = 1'b0;
264                 end
265                 `ALU_CMP: begin
266                         {flag_c, result} = diff;
267                         flag_v = diff_v;
268                         setres = 1'b0;
269                 end
270                 `ALU_CMN: begin
271                         {flag_c, result} = sum;
272                         flag_v = sum_v;
273                         setres = 1'b0;
274                 end
275                 `ALU_ORR: begin
276                         result = in0 | in1;
277                         flag_c = shifter_carry;
278                         setres = 1'b1;
279                 end
280                 `ALU_MOV: begin
281                         result = in1;
282                         flag_c = shifter_carry;
283                         setres = 1'b1;
284                 end
285                 `ALU_BIC: begin
286                         result = in0 & (~in1);
287                         flag_c = shifter_carry;
288                         setres = 1'b1;
289                 end
290                 `ALU_MVN: begin
291                         result = ~in1;
292                         flag_c = shifter_carry;
293                         setres = 1'b1;
294                 end
295                 endcase
296                 
297                 flag_z = (result == 0);
298                 flag_n = result[31];
299                 
300                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
301         end
302 endmodule
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