Execute.v

   1 module Execute(
   2         input clk,
   3         input Nrst,     /* XXX not used yet */
   4
   5         input stall,
   6         input flush,
   7
   8         input inbubble,
   9         input [31:0] pc,
  10         input [31:0] insn,
  11         input [31:0] cpsr,
  12         input [31:0] spsr,
  13         input [31:0] op0,
  14         input [31:0] op1,
  15         input [31:0] op2,
  16         input carry,
  17
  18         output reg outstall = 0,
  19         output reg outbubble = 1,
  20         output reg [31:0] outcpsr = 0,
  21         output reg [31:0] outspsr = 0,
  22         output reg write_reg = 1'bx,
  23         output reg [3:0] write_num = 4'bxxxx,
  24         output reg [31:0] write_data = 32'hxxxxxxxx,
  25         output reg [31:0] outpc
  26         output reg outflush
  27         );
  28
  29         reg mult_start;
  30         reg [31:0] mult_acc0, mult_in0, mult_in1;
  31         wire mult_done;
  32         wire [31:0] mult_result;
  33
  34         reg [31:0] alu_in0, alu_in1;
  35         reg [3:0] alu_op;
  36         reg alu_setflags;
  37         wire [31:0] alu_result, alu_outcpsr;
  38         wire alu_setres;
  39
  40         reg next_outbubble;
  41         reg [31:0] next_outcpsr, next_outspsr;
  42         reg next_write_reg;
  43         reg [3:0] next_write_num;
  44         reg [31:0] next_write_data;
  45
  46         Multiplier multiplier(
  47                 .clk(clk), .Nrst(Nrst),
  48                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
  49                 .in1(mult_in1), .done(mult_done), .result(mult_result));
  50
  51         ALU alu(
  52                 .clk(clk), .Nrst(Nrst),
  53                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
  54                 .setflags(alu_setflags), .shifter_carry(carry),
  55                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
  56
  57         always @(posedge clk)
  58         begin
  59                 if (!stall)
  60                 begin
  61                         outbubble <= next_outbubble;
  62                         outcpsr <= next_outcpsr;
  63                         outspsr <= next_outspsr;
  64                         write_reg <= next_write_reg;
  65                         write_num <= next_write_num;
  66                         write_data <= next_write_data;
  67                 end
  68         end
  69
  70         reg prevstall = 0;
  71         always @(posedge clk)
  72                 prevstall <= outstall;
  73
  74         always @(*)
  75         begin
  76                 outstall = stall;
  77                 next_outbubble = inbubble;
  78                 next_outcpsr = cpsr;
  79                 next_outspsr = spsr;
  80                 next_write_reg = 0;
  81                 next_write_num = 4'hx;
  82                 next_write_data = 32'hxxxxxxxx;
  83
  84                 mult_start = 0;
  85                 mult_acc0 = 32'hxxxxxxxx;
  86                 mult_in0 = 32'hxxxxxxxx;
  87                 mult_in1 = 32'hxxxxxxxx;
  88
  89                 alu_in0 = 32'hxxxxxxxx;
  90                 alu_in1 = 32'hxxxxxxxx;
  91                 alu_op = 4'hx;  /* hax! */
  92                 alu_setflags = 1'bx;
  93
  94                 casez (insn)
  95                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  96                 begin
  97                         if (!prevstall && !inbubble)
  98                         begin
  99                                 mult_start = 1;
 100                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
 101                                 mult_in0 = op1 /* Rm */;
 102                                 mult_in1 = op2 /* Rs */;
 103                                 $display("New MUL instruction");
 104                         end
 105                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
 106                         next_outbubble = inbubble | !mult_done | !prevstall;
 107                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 108                         next_write_reg = 1;
 109                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 110                         next_write_data = mult_result;
 111                 end
 112 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
 113                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 114                 begin
 115                         next_write_reg = 1;
 116                         next_write_num = insn[15:12];
 117                         if (insn[22] /* Ps */)
 118                                 next_write_data = spsr;
 119                         else
 120                                 next_write_data = cpsr;
 121                 end
 122                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 123                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 124                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
 125                         begin
 126                                 if (insn[22] /* Ps */)
 127                                         next_outspsr = {op0[31:29], spsr[28:0]};
 128                                 else
 129                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
 130                         end else begin
 131                                 if (insn[22] /* Ps */)
 132                                         next_outspsr = op0;
 133                                 else
 134                                         next_outcpsr = op0;
 135                         end
 136                 `DECODE_ALU_SWP,        /* Atomic swap */
 137                 `DECODE_ALU_BX,         /* Branch */
 138                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
 139                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 140                 begin end
 141                 `DECODE_ALU:            /* ALU */
 142                 begin
 143                         alu_in0 = op0;
 144                         alu_in1 = op1;
 145                         alu_op = insn[24:21];
 146                         alu_setflags = insn[20] /* S */;
 147
 148                         if (alu_setres) begin
 149                                 next_write_reg = 1;
 150                                 next_write_num = insn[15:12] /* Rd */;
 151                                 next_write_data = alu_result;
 152                         end
 153
 154                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
 155                 end
 156                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
 157                 `DECODE_LDRSTR,         /* Single data transfer */
 158                 `DECODE_LDMSTM:         /* Block data transfer */
 159                 begin end
 160                 `DECODE_BRANCH:
 161                 begin
 162                         outpc = pc + op0;
 163                         if(insn[24]) begin
 164                                 next_write_reg = 1;
 165                                 next_write_num = 4'hE; /* link register */
 166                                 next_write_data = pc + 32'h4;
 167                         end
 168                 end                     /* Branch */
 169                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
 170                 `DECODE_CDP,            /* Coprocessor data op */
 171                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
 172                 `DECODE_SWI:            /* SWI */
 173                 begin end
 174                 default:                /* X everything else out */
 175                 begin end
 176                 endcase
 177         end
 178 endmodule
 179
 180 module Multiplier(
 181         input clk,
 182         input Nrst,     /* XXX not used yet */
 183
 184         input start,
 185         input [31:0] acc0,
 186         input [31:0] in0,
 187         input [31:0] in1,
 188
 189         output reg done = 0,
 190         output reg [31:0] result);
 191
 192         reg [31:0] bitfield;
 193         reg [31:0] multiplicand;
 194         reg [31:0] acc;
 195
 196         always @(posedge clk)
 197         begin
 198                 if (start) begin
 199                         bitfield <= in0;
 200                         multiplicand <= in1;
 201                         acc <= acc0;
 202                         done <= 0;
 203                 end else begin
 204                         bitfield <= {2'b00, bitfield[31:2]};
 205                         multiplicand <= {multiplicand[29:0], 2'b00};
 206                         acc <= acc +
 207                                 (bitfield[0] ? multiplicand : 0) +
 208                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
 209                         if (bitfield == 0) begin
 210                                 result <= acc;
 211                                 done <= 1;
 212                         end
 213                 end
 214         end
 215 endmodule
 216
 217 module ALU(
 218         input clk,
 219         input Nrst,     /* XXX not used yet */
 220
 221         input [31:0] in0,
 222         input [31:0] in1,
 223         input [31:0] cpsr,
 224         input [3:0] op,
 225         input setflags,
 226         input shifter_carry,
 227
 228         output reg [31:0] result,
 229         output reg [31:0] cpsr_out,
 230         output reg setres
 231 );
 232         wire [31:0] res;
 233         wire flag_n, flag_z, flag_c, flag_v, setres;
 234         wire [32:0] sum, diff, rdiff;
 235         wire sum_v, diff_v, rdiff_v;
 236
 237         assign sum = {1'b0, in0} + {1'b0, in1};
 238         assign diff = {1'b0, in0} - {1'b0, in1};
 239         assign rdiff = {1'b0, in1} + {1'b0, in0};
 240         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 241         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 242         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 243
 244         always @(*) begin
 245                 res = 32'hxxxxxxxx;
 246                 setres = 1'bx;
 247                 flag_c = cpsr[`CPSR_C];
 248                 flag_v = cpsr[`CPSR_V];
 249                 case(op)
 250                 `ALU_AND: begin
 251                         result = in0 & in1;
 252                         flag_c = shifter_carry;
 253                         setres = 1'b1;
 254                 end
 255                 `ALU_EOR: begin
 256                         result = in0 ^ in1;
 257                         flag_c = shifter_carry;
 258                         setres = 1'b1;
 259                 end
 260                 `ALU_SUB: begin
 261                         {flag_c, result} = diff;
 262                         flag_v = diff_v;
 263                         setres = 1'b1;
 264                 end
 265                 `ALU_RSB: begin
 266                         {flag_c, result} = rdiff;
 267                         flag_v = rdiff_v;
 268                         setres = 1'b1;
 269                 end
 270                 `ALU_ADD: begin
 271                         {flag_c, result} = sum;
 272                         flag_v = sum_v;
 273                         setres = 1'b1;
 274                 end
 275                 `ALU_ADC: begin
 276                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
 277                         flag_v = sum_v | (~sum[31] & result[31]);
 278                         setres = 1'b1;
 279                 end
 280                 `ALU_SBC: begin
 281                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
 282                         flag_v = diff_v | (diff[31] & ~result[31]);
 283                         setres = 1'b1;
 284                 end
 285                 `ALU_RSC: begin
 286                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
 287                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
 288                         setres = 1'b1;
 289                 end
 290                 `ALU_TST: begin
 291                         result = in0 & in1;
 292                         flag_c = shifter_carry;
 293                         setres = 1'b0;
 294                 end
 295                 `ALU_TEQ: begin
 296                         result = in0 ^ in1;
 297                         flag_c = shifter_carry;
 298                         setres = 1'b0;
 299                 end
 300                 `ALU_CMP: begin
 301                         {flag_c, result} = diff;
 302                         flag_v = diff_v;
 303                         setres = 1'b0;
 304                 end
 305                 `ALU_CMN: begin
 306                         {flag_c, result} = sum;
 307                         flag_v = sum_v;
 308                         setres = 1'b0;
 309                 end
 310                 `ALU_ORR: begin
 311                         result = in0 | in1;
 312                         flag_c = shifter_carry;
 313                         setres = 1'b1;
 314                 end
 315                 `ALU_MOV: begin
 316                         result = in1;
 317                         flag_c = shifter_carry;
 318                         setres = 1'b1;
 319                 end
 320                 `ALU_BIC: begin
 321                         result = in0 & (~in1);
 322                         flag_c = shifter_carry;
 323                         setres = 1'b1;
 324                 end
 325                 `ALU_MVN: begin
 326                         result = ~in1;
 327                         flag_c = shifter_carry;
 328                         setres = 1'b1;
 329                 end
 330                 endcase
 331
 332                 flag_z = (result == 0);
 333                 flag_n = result[31];
 334
 335                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
 336         end
 337 endmodule