Execute.v

   1 module Execute(
   2         input clk,
   3         input Nrst,     /* XXX not used yet */
   4
   5         input stall,
   6         input flush,
   7
   8         input inbubble,
   9         input [31:0] pc,
  10         input [31:0] insn,
  11         input [31:0] cpsr,
  12         input [31:0] spsr,
  13         input [31:0] op0,
  14         input [31:0] op1,
  15         input [31:0] op2,
  16         input carry,
  17
  18         output reg outstall = 0,
  19         output reg outbubble = 1,
  20         output reg [31:0] outcpsr = 0,
  21         output reg [31:0] outspsr = 0,
  22         output reg write_reg = 1'bx,
  23         output reg [3:0] write_num = 4'bxxxx,
  24         output reg [31:0] write_data = 32'hxxxxxxxx,
  25         output reg [31:0] jmppc,
  26         output reg jmp
  27         );
  28
  29         reg mult_start;
  30         reg [31:0] mult_acc0, mult_in0, mult_in1;
  31         wire mult_done;
  32         wire [31:0] mult_result;
  33
  34         reg [31:0] alu_in0, alu_in1;
  35         reg [3:0] alu_op;
  36         reg alu_setflags;
  37         wire [31:0] alu_result, alu_outcpsr;
  38         wire alu_setres;
  39
  40         reg next_outbubble;
  41         reg [31:0] next_outcpsr, next_outspsr;
  42         reg next_write_reg;
  43         reg [3:0] next_write_num;
  44
  45         reg [31:0] next_write_data;
  46
  47         Multiplier multiplier(
  48                 .clk(clk), .Nrst(Nrst),
  49                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
  50                 .in1(mult_in1), .done(mult_done), .result(mult_result));
  51
  52         ALU alu(
  53                 .clk(clk), .Nrst(Nrst),
  54                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
  55                 .setflags(alu_setflags), .shifter_carry(carry),
  56                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
  57
  58         always @(posedge clk)
  59         begin
  60                 if (!stall)
  61                 begin
  62                         outbubble <= next_outbubble;
  63                         outcpsr <= next_outcpsr;
  64                         outspsr <= next_outspsr;
  65                         write_reg <= next_write_reg;
  66                         write_num <= next_write_num;
  67                         write_data <= next_write_data;
  68                 end
  69         end
  70
  71         reg prevstall = 0;
  72         always @(posedge clk)
  73                 prevstall <= outstall;
  74
  75         always @(*)
  76         begin
  77                 outstall = stall;
  78                 next_outbubble = inbubble | flush;
  79                 next_outcpsr = cpsr;
  80                 next_outspsr = spsr;
  81                 next_write_reg = 0;
  82                 next_write_num = 4'hx;
  83                 next_write_data = 32'hxxxxxxxx;
  84
  85                 mult_start = 0;
  86                 mult_acc0 = 32'hxxxxxxxx;
  87                 mult_in0 = 32'hxxxxxxxx;
  88                 mult_in1 = 32'hxxxxxxxx;
  89
  90                 alu_in0 = 32'hxxxxxxxx;
  91                 alu_in1 = 32'hxxxxxxxx;
  92                 alu_op = 4'hx;  /* hax! */
  93                 alu_setflags = 1'bx;
  94
  95                 jmp = 1'b0;
  96                 jmppc = 32'hxxxxxxxx;
  97
  98                 casez (insn)
  99                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 100                 begin
 101                         if (!prevstall && !inbubble)
 102                         begin
 103                                 mult_start = 1;
 104                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
 105                                 mult_in0 = op1 /* Rm */;
 106                                 mult_in1 = op2 /* Rs */;
 107                                 $display("New MUL instruction");
 108                         end
 109                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
 110                         next_outbubble = inbubble | !mult_done | !prevstall;
 111                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 112                         next_write_reg = 1;
 113                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 114                         next_write_data = mult_result;
 115                 end
 116 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
 117                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 118                 begin
 119                         next_write_reg = 1;
 120                         next_write_num = insn[15:12];
 121                         if (insn[22] /* Ps */)
 122                                 next_write_data = spsr;
 123                         else
 124                                 next_write_data = cpsr;
 125                 end
 126                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 127                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 128                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
 129                         begin
 130                                 if (insn[22] /* Ps */)
 131                                         next_outspsr = {op0[31:29], spsr[28:0]};
 132                                 else
 133                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
 134                         end else begin
 135                                 if (insn[22] /* Ps */)
 136                                         next_outspsr = op0;
 137                                 else
 138                                         next_outcpsr = op0;
 139                         end
 140                 `DECODE_ALU_SWP,        /* Atomic swap */
 141                 `DECODE_ALU_BX,         /* Branch */
 142                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
 143                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 144                 begin end
 145                 `DECODE_ALU:            /* ALU */
 146                 begin
 147                         alu_in0 = op0;
 148                         alu_in1 = op1;
 149                         alu_op = insn[24:21];
 150                         alu_setflags = insn[20] /* S */;
 151
 152                         if (alu_setres) begin
 153                                 next_write_reg = 1;
 154                                 next_write_num = insn[15:12] /* Rd */;
 155                                 next_write_data = alu_result;
 156                         end
 157
 158                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
 159                 end
 160                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
 161                 `DECODE_LDRSTR,         /* Single data transfer */
 162                 `DECODE_LDMSTM:         /* Block data transfer */
 163                 begin end
 164                 `DECODE_BRANCH:
 165                 begin
 166                         if(!inbubble) begin
 167                                 jmppc = pc + op0 + 32'h8;
 168                                 if(insn[24]) begin
 169                                         next_write_reg = 1;
 170                                         next_write_num = 4'hE; /* link register */
 171                                         next_write_data = pc - 32'h4;
 172                                 end
 173                                 jmp = 1'b1;
 174                         end
 175                 end                     /* Branch */
 176                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
 177                 `DECODE_CDP,            /* Coprocessor data op */
 178                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
 179                 `DECODE_SWI:            /* SWI */
 180                 begin end
 181                 default:                /* X everything else out */
 182                 begin end
 183                 endcase
 184         end
 185 endmodule
 186
 187 module Multiplier(
 188         input clk,
 189         input Nrst,     /* XXX not used yet */
 190
 191         input start,
 192         input [31:0] acc0,
 193         input [31:0] in0,
 194         input [31:0] in1,
 195
 196         output reg done = 0,
 197         output reg [31:0] result);
 198
 199         reg [31:0] bitfield;
 200         reg [31:0] multiplicand;
 201         reg [31:0] acc;
 202
 203         always @(posedge clk)
 204         begin
 205                 if (start) begin
 206                         bitfield <= in0;
 207                         multiplicand <= in1;
 208                         acc <= acc0;
 209                         done <= 0;
 210                 end else begin
 211                         bitfield <= {2'b00, bitfield[31:2]};
 212                         multiplicand <= {multiplicand[29:0], 2'b00};
 213                         acc <= acc +
 214                                 (bitfield[0] ? multiplicand : 0) +
 215                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
 216                         if (bitfield == 0) begin
 217                                 result <= acc;
 218                                 done <= 1;
 219                         end
 220                 end
 221         end
 222 endmodule
 223
 224 module ALU(
 225         input clk,
 226         input Nrst,     /* XXX not used yet */
 227
 228         input [31:0] in0,
 229         input [31:0] in1,
 230         input [31:0] cpsr,
 231         input [3:0] op,
 232         input setflags,
 233         input shifter_carry,
 234
 235         output reg [31:0] result,
 236         output reg [31:0] cpsr_out,
 237         output reg setres
 238 );
 239         reg [31:0] res;
 240         reg flag_n, flag_z, flag_c, flag_v;
 241         wire [32:0] sum, diff, rdiff;
 242         wire sum_v, diff_v, rdiff_v;
 243
 244         assign sum = {1'b0, in0} + {1'b0, in1};
 245         assign diff = {1'b0, in0} - {1'b0, in1};
 246         assign rdiff = {1'b0, in1} + {1'b0, in0};
 247         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 248         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 249         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 250
 251         always @(*) begin
 252                 res = 32'hxxxxxxxx;
 253                 setres = 1'bx;
 254                 flag_c = cpsr[`CPSR_C];
 255                 flag_v = cpsr[`CPSR_V];
 256                 case(op)
 257                 `ALU_AND: begin
 258                         result = in0 & in1;
 259                         flag_c = shifter_carry;
 260                         setres = 1'b1;
 261                 end
 262                 `ALU_EOR: begin
 263                         result = in0 ^ in1;
 264                         flag_c = shifter_carry;
 265                         setres = 1'b1;
 266                 end
 267                 `ALU_SUB: begin
 268                         {flag_c, result} = diff;
 269                         flag_v = diff_v;
 270                         setres = 1'b1;
 271                 end
 272                 `ALU_RSB: begin
 273                         {flag_c, result} = rdiff;
 274                         flag_v = rdiff_v;
 275                         setres = 1'b1;
 276                 end
 277                 `ALU_ADD: begin
 278                         {flag_c, result} = sum;
 279                         flag_v = sum_v;
 280                         setres = 1'b1;
 281                 end
 282                 `ALU_ADC: begin
 283                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
 284                         flag_v = sum_v | (~sum[31] & result[31]);
 285                         setres = 1'b1;
 286                 end
 287                 `ALU_SBC: begin
 288                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
 289                         flag_v = diff_v | (diff[31] & ~result[31]);
 290                         setres = 1'b1;
 291                 end
 292                 `ALU_RSC: begin
 293                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
 294                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
 295                         setres = 1'b1;
 296                 end
 297                 `ALU_TST: begin
 298                         result = in0 & in1;
 299                         flag_c = shifter_carry;
 300                         setres = 1'b0;
 301                 end
 302                 `ALU_TEQ: begin
 303                         result = in0 ^ in1;
 304                         flag_c = shifter_carry;
 305                         setres = 1'b0;
 306                 end
 307                 `ALU_CMP: begin
 308                         {flag_c, result} = diff;
 309                         flag_v = diff_v;
 310                         setres = 1'b0;
 311                 end
 312                 `ALU_CMN: begin
 313                         {flag_c, result} = sum;
 314                         flag_v = sum_v;
 315                         setres = 1'b0;
 316                 end
 317                 `ALU_ORR: begin
 318                         result = in0 | in1;
 319                         flag_c = shifter_carry;
 320                         setres = 1'b1;
 321                 end
 322                 `ALU_MOV: begin
 323                         result = in1;
 324                         flag_c = shifter_carry;
 325                         setres = 1'b1;
 326                 end
 327                 `ALU_BIC: begin
 328                         result = in0 & (~in1);
 329                         flag_c = shifter_carry;
 330                         setres = 1'b1;
 331                 end
 332                 `ALU_MVN: begin
 333                         result = ~in1;
 334                         flag_c = shifter_carry;
 335                         setres = 1'b1;
 336                 end
 337                 endcase
 338
 339                 flag_z = (result == 0);
 340                 flag_n = result[31];
 341
 342                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
 343         end
 344 endmodule