Hit all with the integrate.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 Jan 2009 09:01:50 +0000 (04:01 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 Jan 2009 09:01:50 +0000 (04:01 -0500)
Decode.v
Execute.v
Memory.v
RegFile.v
system.v

index 90ac3d6..b541046 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -10,6 +10,7 @@ module Decode(
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,
+       output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
 
        output reg [3:0] read_0,
@@ -225,6 +226,7 @@ module Decode(
                op1 <= op1_out; /* 'operand 2' - Rm */
                op2 <= op2_out;   /* thirdedge - Rs */
                carry <= carry_out;
+               outcpsr <= incpsr;
                outspsr <= inspsr;
        end
 
index 7f4cf6c..38a192f 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -101,7 +101,7 @@ module Execute(
                alu_setflags = 1'bx;
 
                jmp = 1'b0;
-               jmppc = 32'hxxxxxxxx;
+               jmppc = 32'h00000000;
 
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
index 696b1a4..eb0f69f 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
        input clk,
        input Nrst,
 
+       input flush,
+
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@ -45,8 +47,8 @@ module Memory(
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
-       output reg [31:0] out_spsr = 32'hxxxxxxxx,
-       output reg [31:0] out_cpsr = 32'hxxxxxxxx
+       output reg [31:0] outspsr = 32'hxxxxxxxx,
+       output reg [31:0] outcpsr = 32'hxxxxxxxx
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
@@ -80,8 +82,8 @@ module Memory(
                prev_reg <= cur_reg;
                prev_offset <= offset;
                prev_raddr <= raddr;
-               out_cpsr <= next_outcpsr;
-               out_spsr <= spsr;
+               outcpsr <= next_outcpsr;
+               outspsr <= spsr;
                swp_state <= next_swp_state;
        end
 
@@ -104,7 +106,7 @@ module Memory(
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
-               next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+               next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
                next_swp_oldval = swp_oldval;
@@ -113,7 +115,9 @@ module Memory(
 
                /* XXX shit not given about endianness */
                /* TODO ldrh/strh */
-               casez(insn)
+               if (flush)
+                       next_outbubble = 1'b1;
+               else casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
index 1e94174..730a620 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -9,8 +9,8 @@ module RegFile(
        input [3:0] read_3,
        output reg [31:0] rdata_3,
        output reg [31:0] spsr,
-       input [3:0] write,
-       input write_req,
+       input write,
+       input [3:0] write_reg,
        input [31:0] write_data
        );
        
@@ -37,22 +37,22 @@ module RegFile(
        
        always @(*)
        begin
-               if ((read_0 == write) && write_req)
+               if ((read_0 == write_reg) && write)
                        rdata_0 = write_data;
                else
                        rdata_0 = regfile[read_0];
                
-               if ((read_1 == write) && write_req)
+               if ((read_1 == write_reg) && write)
                        rdata_1 = write_data;
                else
                        rdata_1 = regfile[read_1];
                
-               if ((read_2 == write) && write_req)
+               if ((read_2 == write_reg) && write)
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
 
-               if ((read_3 == write) && write_req)
+               if ((read_3 == write_reg) && write)
                        rdata_3 = write_data;
                else
                        rdata_3 = regfile[read_3];
@@ -61,6 +61,6 @@ module RegFile(
        end
        
        always @(posedge clk)
-               if (write_req)
-                       regfile[write] <= write_data;
+               if (write)
+                       regfile[write_reg] <= write_data;
 endmodule
index ddbe0b7..d7fc62c 100644 (file)
--- a/system.v
+++ b/system.v
@@ -46,23 +46,32 @@ module System(input clk);
        wire dcache_rw_wait;
        wire [31:0] dcache_wr_data, dcache_rd_data;
        
-       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
+       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
        wire decode_out_carry;
        
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
        wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
+       wire regfile_write;
+       wire [3:0] regfile_write_reg;
+       wire [31:0] regfile_write_data;
        
        wire execute_out_write_reg;
        wire [3:0] execute_out_write_num;
        wire [31:0] execute_out_write_data;
        wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
        wire [31:0] execute_out_cpsr, execute_out_spsr;
-       wire [31:0] jmppc;
-       wire jmp;
+       
+       wire jmp_out_execute, jmp_out_writeback;
+       wire [31:0] jmppc_out_execute, jmppc_out_writeback;
+       wire jmp = jmp_out_execute | jmp_out_writeback;
+       wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
        
        wire memory_out_write_reg;
        wire [3:0] memory_out_write_num;
        wire [31:0] memory_out_write_data;
+       wire [31:0] memory_out_cpsr, memory_out_spsr;
+       
+       wire [31:0] writeback_out_cpsr, writeback_out_spsr;
 
        wire cp_ack_terminal;
        wire cp_busy_terminal;
@@ -93,6 +102,7 @@ module System(input clk);
        wire [31:0] pc_out_memory;
 
        wire execute_out_backflush;
+       wire writeback_out_backflush;
 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
@@ -133,9 +143,9 @@ module System(input clk);
        Issue issue(
                .clk(clk),
                .Nrst(1'b1 /* XXX */),
-               .stall(stall_cause_execute), .flush(execute_out_backflush),
+               .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
                .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
-               .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
+               .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
                .outpc(pc_out_issue), .outinsn(insn_out_issue));
        
@@ -143,26 +153,27 @@ module System(input clk);
                .clk(clk),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
-               .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
+               .spsr(regfile_spsr),
+               .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
        
        Decode decode(
                .clk(clk),
-               .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
+               .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
-               .carry(decode_out_carry), .outspsr(decode_out_spsr),
+               .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        
        Execute execute(
                .clk(clk), .Nrst(1'b0),
-               .stall(stall_cause_memory), .flush(1'b0),
+               .stall(stall_cause_memory), .flush(writeback_out_backflush),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
-               .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
+               .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
                .op2(decode_out_op2), .carry(decode_out_carry),
                .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
                .write_data(execute_out_write_data),
-               .jmp(jmp), .jmppc(jmppc),
+               .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
                .outpc(pc_out_execute), .outinsn(insn_out_execute),
                .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
                .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
@@ -171,7 +182,7 @@ module System(input clk);
        assign cp_insn = insn_out_execute;
        Memory memory(
                .clk(clk), .Nrst(1'b0),
-               /* stall? flush? */
+               /* stall? */ .flush(writeback_out_backflush),
                .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
                .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
                .st_read(regfile_read_3), .st_data(regfile_rdata_3),
@@ -183,12 +194,23 @@ module System(input clk);
                .outpc(pc_out_memory), .outinsn(insn_out_memory),
                .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
                .out_write_data(memory_out_write_data),
-               .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write));
+               .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
+               .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr));
        
        Terminal terminal(      
                .clk(clk),
                .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
                .cp_read(cp_read_terminal), .cp_write(cp_write));
+       
+       Writeback writeback(
+               .clk(clk),
+               .inbubble(bubble_out_memory),
+               .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
+               .cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
+               .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
+               .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
+               .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
+       assign writeback_out_backflush = jmp_out_writeback;
 
        reg [31:0] clockno = 0;
        always @(posedge clk)
@@ -200,5 +222,6 @@ module System(input clk);
                $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
                $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
                $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
+               $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
        end
 endmodule
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