added branch support, maybe
[firearm.git] / Execute.v
1 module Execute(
2         input clk,
3         input Nrst,     /* XXX not used yet */
4         
5         input stall,
6         input flush,
7         
8         input inbubble,
9         input [31:0] pc,
10         input [31:0] insn,
11         input [31:0] cpsr,
12         input [31:0] spsr,
13         input [31:0] op0,
14         input [31:0] op1,
15         input [31:0] op2,
16         input carry,
17         
18         output reg outstall = 0,
19         output reg outbubble = 1,
20         output reg [31:0] outcpsr = 0,
21         output reg [31:0] outspsr = 0,
22         output reg write_reg = 1'bx,
23         output reg [3:0] write_num = 4'bxxxx,
24         output reg [31:0] write_data = 32'hxxxxxxxx,
25         output reg [31:0] jmppc,
26         output reg jmp
27         );
28         
29         reg mult_start;
30         reg [31:0] mult_acc0, mult_in0, mult_in1;
31         wire mult_done;
32         wire [31:0] mult_result;
33         
34         reg [31:0] alu_in0, alu_in1;
35         reg [3:0] alu_op;
36         reg alu_setflags;
37         wire [31:0] alu_result, alu_outcpsr;
38         wire alu_setres;
39         
40         reg next_outbubble;
41         reg [31:0] next_outcpsr, next_outspsr;
42         reg next_write_reg;
43         reg [3:0] next_write_num;
44
45         reg [31:0] next_write_data;
46
47         Multiplier multiplier(
48                 .clk(clk), .Nrst(Nrst),
49                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
50                 .in1(mult_in1), .done(mult_done), .result(mult_result));
51         
52         ALU alu(
53                 .clk(clk), .Nrst(Nrst),
54                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
55                 .setflags(alu_setflags), .shifter_carry(carry),
56                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
57         
58         always @(posedge clk)
59         begin
60                 if (!stall)
61                 begin
62                         outbubble <= next_outbubble;
63                         outcpsr <= next_outcpsr;
64                         outspsr <= next_outspsr;
65                         write_reg <= next_write_reg;
66                         write_num <= next_write_num;
67                         write_data <= next_write_data;
68                 end
69         end
70
71         reg prevstall = 0;
72         always @(posedge clk)
73                 prevstall <= outstall;
74
75         always @(*)
76         begin
77                 outstall = stall;
78                 next_outbubble = inbubble | flush;
79                 next_outcpsr = cpsr;
80                 next_outspsr = spsr;
81                 next_write_reg = 0;
82                 next_write_num = 4'hx;
83                 next_write_data = 32'hxxxxxxxx;
84
85                 mult_start = 0;
86                 mult_acc0 = 32'hxxxxxxxx;
87                 mult_in0 = 32'hxxxxxxxx;
88                 mult_in1 = 32'hxxxxxxxx;
89
90                 alu_in0 = 32'hxxxxxxxx;
91                 alu_in1 = 32'hxxxxxxxx;
92                 alu_op = 4'hx;  /* hax! */
93                 alu_setflags = 1'bx;
94
95                 jmp = 1'b0;
96                 jmppc = 32'hxxxxxxxx;
97
98                 casez (insn)
99                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
100                 begin
101                         if (!prevstall && !inbubble)
102                         begin
103                                 mult_start = 1;
104                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
105                                 mult_in0 = op1 /* Rm */;
106                                 mult_in1 = op2 /* Rs */;
107                                 $display("New MUL instruction");
108                         end
109                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
110                         next_outbubble = inbubble | !mult_done | !prevstall;
111                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
112                         next_write_reg = 1;
113                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
114                         next_write_data = mult_result;
115                 end
116 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
117                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
118                 begin
119                         next_write_reg = 1;
120                         next_write_num = insn[15:12];
121                         if (insn[22] /* Ps */)
122                                 next_write_data = spsr;
123                         else
124                                 next_write_data = cpsr;
125                 end
126                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
127                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
128                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
129                         begin
130                                 if (insn[22] /* Ps */)
131                                         next_outspsr = {op0[31:29], spsr[28:0]};
132                                 else
133                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
134                         end else begin
135                                 if (insn[22] /* Ps */)
136                                         next_outspsr = op0;
137                                 else
138                                         next_outcpsr = op0;
139                         end
140                 `DECODE_ALU_SWP,        /* Atomic swap */
141                 `DECODE_ALU_BX,         /* Branch */
142                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
143                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
144                 begin end
145                 `DECODE_ALU:            /* ALU */
146                 begin
147                         alu_in0 = op0;
148                         alu_in1 = op1;
149                         alu_op = insn[24:21];
150                         alu_setflags = insn[20] /* S */;
151                         
152                         if (alu_setres) begin
153                                 next_write_reg = 1;
154                                 next_write_num = insn[15:12] /* Rd */;
155                                 next_write_data = alu_result;
156                         end
157                         
158                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
159                 end
160                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
161                 `DECODE_LDRSTR,         /* Single data transfer */
162                 `DECODE_LDMSTM:         /* Block data transfer */
163                 begin end
164                 `DECODE_BRANCH:
165                 begin
166                         jmppc = pc + op0 + 32'h8;
167                         if(insn[24]) begin
168                                 next_write_reg = 1;
169                                 next_write_num = 4'hE; /* link register */
170                                 next_write_data = pc + 32'h4;
171                         end
172                         jmp = 1'b1;
173                 end                     /* Branch */
174                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
175                 `DECODE_CDP,            /* Coprocessor data op */
176                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
177                 `DECODE_SWI:            /* SWI */
178                 begin end
179                 default:                /* X everything else out */
180                 begin end
181                 endcase
182         end
183 endmodule
184
185 module Multiplier(
186         input clk,
187         input Nrst,     /* XXX not used yet */
188         
189         input start,
190         input [31:0] acc0,
191         input [31:0] in0,
192         input [31:0] in1,
193         
194         output reg done = 0,
195         output reg [31:0] result);
196         
197         reg [31:0] bitfield;
198         reg [31:0] multiplicand;
199         reg [31:0] acc;
200         
201         always @(posedge clk)
202         begin
203                 if (start) begin
204                         bitfield <= in0;
205                         multiplicand <= in1;
206                         acc <= acc0;
207                         done <= 0;
208                 end else begin
209                         bitfield <= {2'b00, bitfield[31:2]};
210                         multiplicand <= {multiplicand[29:0], 2'b00};
211                         acc <= acc +
212                                 (bitfield[0] ? multiplicand : 0) +
213                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
214                         if (bitfield == 0) begin
215                                 result <= acc;
216                                 done <= 1;
217                         end
218                 end
219         end
220 endmodule
221
222 module ALU(
223         input clk,
224         input Nrst,     /* XXX not used yet */
225
226         input [31:0] in0,
227         input [31:0] in1,
228         input [31:0] cpsr,
229         input [3:0] op,
230         input setflags,
231         input shifter_carry,
232
233         output reg [31:0] result,
234         output reg [31:0] cpsr_out,
235         output reg setres
236 );
237         wire [31:0] res;
238         wire flag_n, flag_z, flag_c, flag_v, setres;
239         wire [32:0] sum, diff, rdiff;
240         wire sum_v, diff_v, rdiff_v;
241
242         assign sum = {1'b0, in0} + {1'b0, in1};
243         assign diff = {1'b0, in0} - {1'b0, in1};
244         assign rdiff = {1'b0, in1} + {1'b0, in0};
245         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
246         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
247         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
248
249         always @(*) begin
250                 res = 32'hxxxxxxxx;
251                 setres = 1'bx;
252                 flag_c = cpsr[`CPSR_C];
253                 flag_v = cpsr[`CPSR_V];
254                 case(op)
255                 `ALU_AND: begin
256                         result = in0 & in1;
257                         flag_c = shifter_carry;
258                         setres = 1'b1;
259                 end
260                 `ALU_EOR: begin
261                         result = in0 ^ in1;
262                         flag_c = shifter_carry;
263                         setres = 1'b1;
264                 end
265                 `ALU_SUB: begin
266                         {flag_c, result} = diff;
267                         flag_v = diff_v;
268                         setres = 1'b1;
269                 end
270                 `ALU_RSB: begin
271                         {flag_c, result} = rdiff;
272                         flag_v = rdiff_v;
273                         setres = 1'b1;
274                 end
275                 `ALU_ADD: begin
276                         {flag_c, result} = sum;
277                         flag_v = sum_v;
278                         setres = 1'b1;
279                 end
280                 `ALU_ADC: begin
281                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
282                         flag_v = sum_v | (~sum[31] & result[31]);
283                         setres = 1'b1;
284                 end
285                 `ALU_SBC: begin
286                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
287                         flag_v = diff_v | (diff[31] & ~result[31]);
288                         setres = 1'b1;
289                 end
290                 `ALU_RSC: begin
291                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
292                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
293                         setres = 1'b1;
294                 end
295                 `ALU_TST: begin
296                         result = in0 & in1;
297                         flag_c = shifter_carry;
298                         setres = 1'b0;
299                 end
300                 `ALU_TEQ: begin
301                         result = in0 ^ in1;
302                         flag_c = shifter_carry;
303                         setres = 1'b0;
304                 end
305                 `ALU_CMP: begin
306                         {flag_c, result} = diff;
307                         flag_v = diff_v;
308                         setres = 1'b0;
309                 end
310                 `ALU_CMN: begin
311                         {flag_c, result} = sum;
312                         flag_v = sum_v;
313                         setres = 1'b0;
314                 end
315                 `ALU_ORR: begin
316                         result = in0 | in1;
317                         flag_c = shifter_carry;
318                         setres = 1'b1;
319                 end
320                 `ALU_MOV: begin
321                         result = in1;
322                         flag_c = shifter_carry;
323                         setres = 1'b1;
324                 end
325                 `ALU_BIC: begin
326                         result = in0 & (~in1);
327                         flag_c = shifter_carry;
328                         setres = 1'b1;
329                 end
330                 `ALU_MVN: begin
331                         result = ~in1;
332                         flag_c = shifter_carry;
333                         setres = 1'b1;
334                 end
335                 endcase
336                 
337                 flag_z = (result == 0);
338                 flag_n = result[31];
339                 
340                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
341         end
342 endmodule
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