Merge nyus:/storage/git/firearm
[firearm.git] / Execute.v
1 module Execute(
2         input clk,
3         input Nrst,     /* XXX not used yet */
4         
5         input stall,
6         input flush,
7         
8         input inbubble,
9         input [31:0] pc,
10         input [31:0] insn,
11         input [31:0] cpsr,
12         input [31:0] op0,
13         input [31:0] op1,
14         input [31:0] op2,
15         input carry,
16         
17         output reg outstall = 0,
18         output reg outbubble = 1,
19         output reg write_reg = 1'bx,
20         output reg [3:0] write_num = 4'bxxxx,
21         output reg [31:0] write_data = 32'hxxxxxxxx
22         );
23         
24         reg mult_start;
25         reg [31:0] mult_acc0, mult_in0, mult_in1;
26         wire mult_done;
27         wire [31:0] mult_result;
28         
29         Multiplier multiplier(
30                 .clk(clk), .Nrst(Nrst),
31                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
32                 .in1(mult_in1), .done(mult_done), .result(mult_result));
33 endmodule
34
35 module Multiplier(
36         input clk,
37         input Nrst,     /* XXX not used yet */
38         
39         input start,
40         input [31:0] acc0,
41         input [31:0] in0,
42         input [31:0] in1,
43         
44         output reg done = 0,
45         output reg [31:0] result);
46         
47         reg [31:0] bitfield;
48         reg [31:0] multiplicand;
49         reg [31:0] acc;
50         
51         always @(posedge clk)
52         begin
53                 if (start) begin
54                         bitfield <= in0;
55                         multiplicand <= in1;
56                         acc <= acc0;
57                         done <= 0;
58                 end else begin
59                         bitfield <= {2'b00, bitfield[31:2]};
60                         multiplicand <= {multiplicand[29:0], 2'b00};
61                         acc <= acc +
62                                 (bitfield[0] ? multiplicand : 0) +
63                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
64                         if (bitfield == 0) begin
65                                 result <= acc;
66                                 done <= 1;
67                         end
68                 end
69         end
70 endmodule
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