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(parent: 6060e53) | patch
Execute.v: Add outpc and outinsn. System.v: Add and make wires consistent.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 03:21:53 +0000 (22:21 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 03:21:53 +0000 (22:21 -0500)
commit2393422aab14e1b2172b4e52b9117272cc13c72e
tree3466a724f2c835d875a6f620dfe0cc990015b6a8tree | snapshot
parent6060e5359241449a70a27ed0d7023951ee21ceebcommit | diff
Execute.v: Add outpc and outinsn. System.v: Add and make wires consistent.
Execute.v diff | blob | blame | history
system.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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