Execute.v

   1 module Execute(
   2         input clk,
   3         input Nrst,     /* XXX not used yet */
   4
   5         input stall,
   6         input flush,
   7
   8         input inbubble,
   9         input [31:0] pc,
  10         input [31:0] insn,
  11         input [31:0] cpsr,
  12         input [31:0] spsr,
  13         input [31:0] op0,
  14         input [31:0] op1,
  15         input [31:0] op2,
  16         input carry,
  17
  18         output reg outstall = 0,
  19         output reg outbubble = 1,
  20         output reg [31:0] outcpsr = 0,
  21         output reg [31:0] outspsr = 0,
  22         output reg write_reg = 1'bx,
  23         output reg [3:0] write_num = 4'bxxxx,
  24         output reg [31:0] write_data = 32'hxxxxxxxx,
  25         output reg [31:0] jmppc,
  26         output reg jmp,
  27         output reg [31:0] outpc,
  28         output reg [31:0] outinsn,
  29         output reg [31:0] outop0, outop1, outop2
  30         );
  31
  32         reg mult_start;
  33         reg [31:0] mult_acc0, mult_in0, mult_in1;
  34         wire mult_done;
  35         wire [31:0] mult_result;
  36
  37         reg [31:0] alu_in0, alu_in1;
  38         reg [3:0] alu_op;
  39         reg alu_setflags;
  40         wire [31:0] alu_result, alu_outcpsr;
  41         wire alu_setres;
  42
  43         reg next_outbubble;
  44         reg [31:0] next_outcpsr, next_outspsr;
  45         reg next_write_reg;
  46         reg [3:0] next_write_num;
  47
  48         reg [31:0] next_write_data;
  49
  50         Multiplier multiplier(
  51                 .clk(clk), .Nrst(Nrst),
  52                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
  53                 .in1(mult_in1), .done(mult_done), .result(mult_result));
  54
  55         ALU alu(
  56                 .clk(clk), .Nrst(Nrst),
  57                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
  58                 .setflags(alu_setflags), .shifter_carry(carry),
  59                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
  60
  61         always @(posedge clk)
  62         begin
  63                 if (!stall)
  64                 begin
  65                         outbubble <= next_outbubble;
  66                         outcpsr <= next_outcpsr;
  67                         outspsr <= next_outspsr;
  68                         write_reg <= next_write_reg;
  69                         write_num <= next_write_num;
  70                         write_data <= next_write_data;
  71                         outpc <= pc;
  72                         outinsn <= insn;
  73                         outop0 <= op0;
  74                         outop1 <= op1;
  75                         outop2 <= op2;
  76                 end
  77         end
  78
  79         reg prevstall = 0;
  80         always @(posedge clk)
  81                 prevstall <= outstall;
  82
  83         always @(*)
  84         begin
  85                 outstall = stall;
  86                 next_outbubble = inbubble | flush;
  87                 next_outcpsr = cpsr;
  88                 next_outspsr = spsr;
  89                 next_write_reg = 0;
  90                 next_write_num = 4'hx;
  91                 next_write_data = 32'hxxxxxxxx;
  92
  93                 mult_start = 0;
  94                 mult_acc0 = 32'hxxxxxxxx;
  95                 mult_in0 = 32'hxxxxxxxx;
  96                 mult_in1 = 32'hxxxxxxxx;
  97
  98                 alu_in0 = 32'hxxxxxxxx;
  99                 alu_in1 = 32'hxxxxxxxx;
 100                 alu_op = 4'hx;  /* hax! */
 101                 alu_setflags = 1'bx;
 102
 103                 jmp = 1'b0;
 104                 jmppc = 32'h00000000;
 105
 106                 casez (insn)
 107                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 108                 begin
 109                         if (!prevstall && !inbubble)
 110                         begin
 111                                 mult_start = 1;
 112                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
 113                                 mult_in0 = op1 /* Rm */;
 114                                 mult_in1 = op2 /* Rs */;
 115                                 $display("New MUL instruction");
 116                         end
 117                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
 118                         next_outbubble = inbubble | !mult_done | !prevstall;
 119                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 120                         next_write_reg = 1;
 121                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 122                         next_write_data = mult_result;
 123                 end
 124 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
 125                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 126                 begin
 127                         next_write_reg = 1;
 128                         next_write_num = insn[15:12];
 129                         if (insn[22] /* Ps */)
 130                                 next_write_data = spsr;
 131                         else
 132                                 next_write_data = cpsr;
 133                 end
 134                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 135                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 136                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
 137                         begin
 138                                 if (insn[22] /* Ps */)
 139                                         next_outspsr = {op0[31:29], spsr[28:0]};
 140                                 else
 141                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
 142                         end else begin
 143                                 if (insn[22] /* Ps */)
 144                                         next_outspsr = op0;
 145                                 else
 146                                         next_outcpsr = op0;
 147                         end
 148                 `DECODE_ALU_SWP,        /* Atomic swap */
 149                 `DECODE_ALU_BX,         /* Branch */
 150                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
 151                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 152                 begin end
 153                 `DECODE_ALU:            /* ALU */
 154                 begin
 155                         alu_in0 = op0;
 156                         alu_in1 = op1;
 157                         alu_op = insn[24:21];
 158                         alu_setflags = insn[20] /* S */;
 159
 160                         if (alu_setres) begin
 161                                 next_write_reg = 1;
 162                                 next_write_num = insn[15:12] /* Rd */;
 163                                 next_write_data = alu_result;
 164                         end
 165
 166                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
 167                 end
 168                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
 169                 `DECODE_LDRSTR,         /* Single data transfer */
 170                 `DECODE_LDMSTM:         /* Block data transfer */
 171                 begin end
 172                 `DECODE_BRANCH:
 173                 begin
 174                         if(!inbubble && !flush) begin
 175                                 jmppc = pc + op0 + 32'h8;
 176                                 if(insn[24]) begin
 177                                         next_write_reg = 1;
 178                                         next_write_num = 4'hE; /* link register */
 179                                         next_write_data = pc + 32'h4;
 180                                 end
 181                                 jmp = 1'b1;
 182                         end
 183                 end                     /* Branch */
 184                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
 185                 `DECODE_CDP,            /* Coprocessor data op */
 186                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
 187                 `DECODE_SWI:            /* SWI */
 188                 begin end
 189                 default:                /* X everything else out */
 190                 begin end
 191                 endcase
 192         end
 193 endmodule
 194
 195 module Multiplier(
 196         input clk,
 197         input Nrst,     /* XXX not used yet */
 198
 199         input start,
 200         input [31:0] acc0,
 201         input [31:0] in0,
 202         input [31:0] in1,
 203
 204         output reg done = 0,
 205         output reg [31:0] result);
 206
 207         reg [31:0] bitfield;
 208         reg [31:0] multiplicand;
 209         reg [31:0] acc;
 210
 211         always @(posedge clk)
 212         begin
 213                 if (start) begin
 214                         bitfield <= in0;
 215                         multiplicand <= in1;
 216                         acc <= acc0;
 217                         done <= 0;
 218                 end else begin
 219                         bitfield <= {2'b00, bitfield[31:2]};
 220                         multiplicand <= {multiplicand[29:0], 2'b00};
 221                         acc <= acc +
 222                                 (bitfield[0] ? multiplicand : 0) +
 223                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
 224                         if (bitfield == 0) begin
 225                                 result <= acc;
 226                                 done <= 1;
 227                         end
 228                 end
 229         end
 230 endmodule
 231
 232 module ALU(
 233         input clk,
 234         input Nrst,     /* XXX not used yet */
 235
 236         input [31:0] in0,
 237         input [31:0] in1,
 238         input [31:0] cpsr,
 239         input [3:0] op,
 240         input setflags,
 241         input shifter_carry,
 242
 243         output reg [31:0] result,
 244         output reg [31:0] cpsr_out,
 245         output reg setres
 246 );
 247         reg [31:0] res;
 248         reg flag_n, flag_z, flag_c, flag_v;
 249         wire [32:0] sum, diff, rdiff;
 250         wire sum_v, diff_v, rdiff_v;
 251
 252         assign sum = {1'b0, in0} + {1'b0, in1};
 253         assign diff = {1'b0, in0} - {1'b0, in1};
 254         assign rdiff = {1'b0, in1} + {1'b0, in0};
 255         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 256         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 257         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 258
 259         always @(*) begin
 260                 res = 32'hxxxxxxxx;
 261                 setres = 1'bx;
 262                 flag_c = cpsr[`CPSR_C];
 263                 flag_v = cpsr[`CPSR_V];
 264                 case(op)
 265                 `ALU_AND: begin
 266                         result = in0 & in1;
 267                         flag_c = shifter_carry;
 268                         setres = 1'b1;
 269                 end
 270                 `ALU_EOR: begin
 271                         result = in0 ^ in1;
 272                         flag_c = shifter_carry;
 273                         setres = 1'b1;
 274                 end
 275                 `ALU_SUB: begin
 276                         {flag_c, result} = diff;
 277                         flag_v = diff_v;
 278                         setres = 1'b1;
 279                 end
 280                 `ALU_RSB: begin
 281                         {flag_c, result} = rdiff;
 282                         flag_v = rdiff_v;
 283                         setres = 1'b1;
 284                 end
 285                 `ALU_ADD: begin
 286                         {flag_c, result} = sum;
 287                         flag_v = sum_v;
 288                         setres = 1'b1;
 289                 end
 290                 `ALU_ADC: begin
 291                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
 292                         flag_v = sum_v | (~sum[31] & result[31]);
 293                         setres = 1'b1;
 294                 end
 295                 `ALU_SBC: begin
 296                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
 297                         flag_v = diff_v | (diff[31] & ~result[31]);
 298                         setres = 1'b1;
 299                 end
 300                 `ALU_RSC: begin
 301                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
 302                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
 303                         setres = 1'b1;
 304                 end
 305                 `ALU_TST: begin
 306                         result = in0 & in1;
 307                         flag_c = shifter_carry;
 308                         setres = 1'b0;
 309                 end
 310                 `ALU_TEQ: begin
 311                         result = in0 ^ in1;
 312                         flag_c = shifter_carry;
 313                         setres = 1'b0;
 314                 end
 315                 `ALU_CMP: begin
 316                         {flag_c, result} = diff;
 317                         flag_v = diff_v;
 318                         setres = 1'b0;
 319                 end
 320                 `ALU_CMN: begin
 321                         {flag_c, result} = sum;
 322                         flag_v = sum_v;
 323                         setres = 1'b0;
 324                 end
 325                 `ALU_ORR: begin
 326                         result = in0 | in1;
 327                         flag_c = shifter_carry;
 328                         setres = 1'b1;
 329                 end
 330                 `ALU_MOV: begin
 331                         result = in1;
 332                         flag_c = shifter_carry;
 333                         setres = 1'b1;
 334                 end
 335                 `ALU_BIC: begin
 336                         result = in0 & (~in1);
 337                         flag_c = shifter_carry;
 338                         setres = 1'b1;
 339                 end
 340                 `ALU_MVN: begin
 341                         result = ~in1;
 342                         flag_c = shifter_carry;
 343                         setres = 1'b1;
 344                 end
 345                 endcase
 346
 347                 flag_z = (result == 0);
 348                 flag_n = result[31];
 349
 350                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
 351         end
 352 endmodule