Execute.v

   1 module Execute(
   2         input clk,
   3         input Nrst,     /* XXX not used yet */
   4
   5         input stall,
   6         input flush,
   7
   8         input inbubble,
   9         input [31:0] pc,
  10         input [31:0] insn,
  11         input [31:0] cpsr,
  12         input [31:0] spsr,
  13         input [31:0] op0,
  14         input [31:0] op1,
  15         input [31:0] op2,
  16         input carry,
  17
  18         output reg outstall = 0,
  19         output reg outbubble = 1,
  20         output reg [31:0] outcpsr = 0,
  21         output reg [31:0] outspsr = 0,
  22         output reg write_reg = 1'bx,
  23         output reg [3:0] write_num = 4'bxxxx,
  24         output reg [31:0] write_data = 32'hxxxxxxxx
  25         );
  26
  27         reg mult_start;
  28         reg [31:0] mult_acc0, mult_in0, mult_in1;
  29         wire mult_done;
  30         wire [31:0] mult_result;
  31
  32         reg [31:0] alu_in0, alu_in1;
  33         reg [3:0] alu_op;
  34         reg alu_setflags;
  35         wire [31:0] alu_result, alu_outcpsr;
  36         wire alu_setres;
  37
  38         reg next_outbubble;
  39         reg [31:0] next_outcpsr, next_outspsr;
  40         reg next_write_reg;
  41         reg [3:0] next_write_num;
  42         reg [31:0] next_write_data;
  43
  44         Multiplier multiplier(
  45                 .clk(clk), .Nrst(Nrst),
  46                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
  47                 .in1(mult_in1), .done(mult_done), .result(mult_result));
  48
  49         ALU alu(
  50                 .clk(clk), .Nrst(Nrst),
  51                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
  52                 .setflags(alu_setflags), .shifter_carry(carry),
  53                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
  54
  55         always @(posedge clk)
  56         begin
  57                 if (!stall)
  58                 begin
  59                         outbubble <= next_outbubble;
  60                         outcpsr <= next_outcpsr;
  61                         outspsr <= next_outspsr;
  62                         write_reg <= next_write_reg;
  63                         write_num <= next_write_num;
  64                         write_data <= next_write_data;
  65                 end
  66         end
  67
  68         reg prevstall = 0;
  69         always @(posedge clk)
  70                 prevstall <= outstall;
  71
  72         always @(*)
  73         begin
  74                 outstall = stall;
  75                 next_outbubble = inbubble;
  76                 next_outcpsr = cpsr;
  77                 next_outspsr = spsr;
  78                 next_write_reg = 0;
  79                 next_write_num = 4'hx;
  80                 next_write_data = 32'hxxxxxxxx;
  81
  82                 mult_start = 0;
  83                 mult_acc0 = 32'hxxxxxxxx;
  84                 mult_in0 = 32'hxxxxxxxx;
  85                 mult_in1 = 32'hxxxxxxxx;
  86
  87                 alu_in0 = 32'hxxxxxxxx;
  88                 alu_in1 = 32'hxxxxxxxx;
  89                 alu_op = 4'hx;  /* hax! */
  90                 alu_setflags = 1'bx;
  91
  92                 casez (insn)
  93                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  94                 begin
  95                         if (!prevstall && !inbubble)
  96                         begin
  97                                 mult_start = 1;
  98                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
  99                                 mult_in0 = op1 /* Rm */;
 100                                 mult_in1 = op2 /* Rs */;
 101                                 $display("New MUL instruction");
 102                         end
 103                         outstall = stall | ((!prevstall | !mult_done) && !inbubble);
 104                         next_outbubble = inbubble | !mult_done | !prevstall;
 105                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 106                         next_write_reg = 1;
 107                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 108                         next_write_data = mult_result;
 109                 end
 110 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
 111                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 112                 begin
 113                         next_write_reg = 1;
 114                         next_write_num = insn[15:12];
 115                         if (insn[22] /* Ps */)
 116                                 next_write_data = spsr;
 117                         else
 118                                 next_write_data = cpsr;
 119                 end
 120                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 121                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 122                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
 123                         begin
 124                                 if (insn[22] /* Ps */)
 125                                         next_outspsr = {op0[31:29], spsr[28:0]};
 126                                 else
 127                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
 128                         end else begin
 129                                 if (insn[22] /* Ps */)
 130                                         next_outspsr = op0;
 131                                 else
 132                                         next_outcpsr = op0;
 133                         end
 134                 `DECODE_ALU_SWP,        /* Atomic swap */
 135                 `DECODE_ALU_BX,         /* Branch */
 136                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
 137                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 138                 begin end
 139                 `DECODE_ALU:            /* ALU */
 140                 begin
 141                         alu_in0 = op0;
 142                         alu_in1 = op1;
 143                         alu_op = insn[24:21];
 144                         alu_setflags = insn[20] /* S */;
 145
 146                         if (alu_setres) begin
 147                                 next_write_reg = 1;
 148                                 next_write_num = insn[15:12] /* Rd */;
 149                                 next_write_data = alu_result;
 150                         end
 151
 152                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
 153                 end
 154                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
 155                 `DECODE_LDRSTR,         /* Single data transfer */
 156                 `DECODE_LDMSTM,         /* Block data transfer */
 157                 `DECODE_BRANCH,         /* Branch */
 158                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
 159                 `DECODE_CDP,            /* Coprocessor data op */
 160                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
 161                 `DECODE_SWI:            /* SWI */
 162                 begin end
 163                 default:                /* X everything else out */
 164                 begin end
 165                 endcase
 166         end
 167 endmodule
 168
 169 module Multiplier(
 170         input clk,
 171         input Nrst,     /* XXX not used yet */
 172
 173         input start,
 174         input [31:0] acc0,
 175         input [31:0] in0,
 176         input [31:0] in1,
 177
 178         output reg done = 0,
 179         output reg [31:0] result);
 180
 181         reg [31:0] bitfield;
 182         reg [31:0] multiplicand;
 183         reg [31:0] acc;
 184
 185         always @(posedge clk)
 186         begin
 187                 if (start) begin
 188                         bitfield <= in0;
 189                         multiplicand <= in1;
 190                         acc <= acc0;
 191                         done <= 0;
 192                 end else begin
 193                         bitfield <= {2'b00, bitfield[31:2]};
 194                         multiplicand <= {multiplicand[29:0], 2'b00};
 195                         acc <= acc +
 196                                 (bitfield[0] ? multiplicand : 0) +
 197                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
 198                         if (bitfield == 0) begin
 199                                 result <= acc;
 200                                 done <= 1;
 201                         end
 202                 end
 203         end
 204 endmodule
 205
 206 module ALU(
 207         input clk,
 208         input Nrst,     /* XXX not used yet */
 209
 210         input [31:0] in0,
 211         input [31:0] in1,
 212         input [31:0] cpsr,
 213         input [3:0] op,
 214         input setflags,
 215         input shifter_carry,
 216
 217         output reg [31:0] result,
 218         output reg [31:0] cpsr_out,
 219         output reg setres
 220 );
 221         wire [31:0] res;
 222         wire flag_n, flag_z, flag_c, flag_v, setres;
 223         wire [32:0] sum, diff, rdiff;
 224         wire sum_v, diff_v, rdiff_v;
 225
 226         assign sum = {1'b0, in0} + {1'b0, in1};
 227         assign diff = {1'b0, in0} - {1'b0, in1};
 228         assign rdiff = {1'b0, in1} + {1'b0, in0};
 229         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 230         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 231         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
 232
 233         always @(*) begin
 234                 res = 32'hxxxxxxxx;
 235                 setres = 1'bx;
 236                 flag_c = cpsr[`CPSR_C];
 237                 flag_v = cpsr[`CPSR_V];
 238                 case(op)
 239                 `ALU_AND: begin
 240                         result = in0 & in1;
 241                         flag_c = shifter_carry;
 242                         setres = 1'b1;
 243                 end
 244                 `ALU_EOR: begin
 245                         result = in0 ^ in1;
 246                         flag_c = shifter_carry;
 247                         setres = 1'b1;
 248                 end
 249                 `ALU_SUB: begin
 250                         {flag_c, result} = diff;
 251                         flag_v = diff_v;
 252                         setres = 1'b1;
 253                 end
 254                 `ALU_RSB: begin
 255                         {flag_c, result} = rdiff;
 256                         flag_v = rdiff_v;
 257                         setres = 1'b1;
 258                 end
 259                 `ALU_ADD: begin
 260                         {flag_c, result} = sum;
 261                         flag_v = sum_v;
 262                         setres = 1'b1;
 263                 end
 264                 `ALU_ADC: begin
 265                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
 266                         flag_v = sum_v | (~sum[31] & result[31]);
 267                         setres = 1'b1;
 268                 end
 269                 `ALU_SBC: begin
 270                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
 271                         flag_v = diff_v | (diff[31] & ~result[31]);
 272                         setres = 1'b1;
 273                 end
 274                 `ALU_RSC: begin
 275                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
 276                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
 277                         setres = 1'b1;
 278                 end
 279                 `ALU_TST: begin
 280                         result = in0 & in1;
 281                         flag_c = shifter_carry;
 282                         setres = 1'b0;
 283                 end
 284                 `ALU_TEQ: begin
 285                         result = in0 ^ in1;
 286                         flag_c = shifter_carry;
 287                         setres = 1'b0;
 288                 end
 289                 `ALU_CMP: begin
 290                         {flag_c, result} = diff;
 291                         flag_v = diff_v;
 292                         setres = 1'b0;
 293                 end
 294                 `ALU_CMN: begin
 295                         {flag_c, result} = sum;
 296                         flag_v = sum_v;
 297                         setres = 1'b0;
 298                 end
 299                 `ALU_ORR: begin
 300                         result = in0 | in1;
 301                         flag_c = shifter_carry;
 302                         setres = 1'b1;
 303                 end
 304                 `ALU_MOV: begin
 305                         result = in1;
 306                         flag_c = shifter_carry;
 307                         setres = 1'b1;
 308                 end
 309                 `ALU_BIC: begin
 310                         result = in0 & (~in1);
 311                         flag_c = shifter_carry;
 312                         setres = 1'b1;
 313                 end
 314                 `ALU_MVN: begin
 315                         result = ~in1;
 316                         flag_c = shifter_carry;
 317                         setres = 1'b1;
 318                 end
 319                 endcase
 320
 321                 flag_z = (result == 0);
 322                 flag_n = result[31];
 323
 324                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
 325         end
 326 endmodule