Execute: Fix carry flag on subtraction operations.
[firearm.git] / Execute.v
1 module Execute(
2         input clk,
3         input Nrst,     /* XXX not used yet */
4         
5         input stall,
6         input flush,
7         
8         input inbubble,
9         input [31:0] pc,
10         input [31:0] insn,
11         input [31:0] cpsr,
12         input [31:0] spsr,
13         input [31:0] op0,
14         input [31:0] op1,
15         input [31:0] op2,
16         input carry,
17         
18         output reg outstall = 0,
19         output reg outbubble = 1,
20         output reg [31:0] outcpsr = 0,
21         output reg [31:0] outspsr = 0,
22         output reg outcpsrup = 0,
23         output reg write_reg = 1'bx,
24         output reg [3:0] write_num = 4'bxxxx,
25         output reg [31:0] write_data = 32'hxxxxxxxx,
26         output reg [31:0] jmppc,
27         output reg jmp,
28         output reg [31:0] outpc,
29         output reg [31:0] outinsn,
30         output reg [31:0] outop0, outop1, outop2
31         );
32         
33         reg mult_start;
34         reg [31:0] mult_acc0, mult_in0, mult_in1;
35         wire mult_done;
36         wire [31:0] mult_result;
37         
38         reg [31:0] alu_in0, alu_in1;
39         reg [3:0] alu_op;
40         reg alu_setflags;
41         wire [31:0] alu_result, alu_outcpsr;
42         wire alu_setres;
43         
44         reg next_outbubble;
45         reg [31:0] next_outcpsr, next_outspsr;
46         reg next_outcpsrup;
47         reg next_write_reg;
48         reg [3:0] next_write_num;
49
50         reg [31:0] next_write_data;
51
52         Multiplier multiplier(
53                 .clk(clk), .Nrst(Nrst),
54                 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
55                 .in1(mult_in1), .done(mult_done), .result(mult_result));
56         
57         ALU alu(
58                 .clk(clk), .Nrst(Nrst),
59                 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
60                 .setflags(alu_setflags), .shifter_carry(carry),
61                 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
62
63         always @(posedge clk)
64         begin
65                 if (!stall)
66                 begin
67                         outbubble <= next_outbubble;
68                         outcpsr <= next_outcpsr;
69                         outspsr <= next_outspsr;
70                         outcpsrup <= next_outcpsrup;
71                         write_reg <= next_write_reg;
72                         write_num <= next_write_num;
73                         write_data <= next_write_data;
74                         outpc <= pc;
75                         outinsn <= insn;
76                         outop0 <= op0;
77                         outop1 <= op1;
78                         outop2 <= op2;
79                 end
80         end
81         
82         reg delayedflush = 0;
83         always @(posedge clk)
84                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
85                         delayedflush <= 1;
86                 else if (!outstall /* anything has been handled this time around */)
87                         delayedflush <= 0;
88
89         reg prevstall = 0;
90         always @(posedge clk)
91                 prevstall <= outstall;
92
93         always @(*)
94         begin
95                 outstall = stall;
96                 next_outbubble = inbubble | flush | delayedflush;
97                 next_outcpsr = cpsr;
98                 next_outspsr = spsr;
99                 next_outcpsrup = 0;
100                 next_write_reg = 0;
101                 next_write_num = 4'hx;
102                 next_write_data = 32'hxxxxxxxx;
103
104                 mult_start = 0;
105                 mult_acc0 = 32'hxxxxxxxx;
106                 mult_in0 = 32'hxxxxxxxx;
107                 mult_in1 = 32'hxxxxxxxx;
108
109                 alu_in0 = 32'hxxxxxxxx;
110                 alu_in1 = 32'hxxxxxxxx;
111                 alu_op = 4'hx;  /* hax! */
112                 alu_setflags = 1'bx;
113
114                 jmp = 1'b0;
115                 jmppc = 32'h00000000;
116
117                 casez (insn)
118                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
119                 begin
120                         if (!prevstall && !inbubble)
121                         begin
122                                 mult_start = 1;
123                                 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
124                                 mult_in0 = op1 /* Rm */;
125                                 mult_in1 = op2 /* Rs */;
126                                 $display("New MUL instruction");
127                         end
128                         outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
129                         next_outbubble = next_outbubble | !mult_done | !prevstall;
130                         next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
131                         next_outcpsrup = insn[20] /* S */;
132                         next_write_reg = 1;
133                         next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
134                         next_write_data = mult_result;
135                 end
136 //              `DECODE_ALU_MUL_LONG,   /* Multiply long */
137                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
138                 begin
139                         next_write_reg = 1;
140                         next_write_num = insn[15:12];
141                         if (insn[22] /* Ps */)
142                                 next_write_data = spsr;
143                         else
144                                 next_write_data = cpsr;
145                         next_outcpsrup = 1;
146                 end
147                 `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
148                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
149                 begin
150                         if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
151                         begin
152                                 if (insn[22] /* Ps */)
153                                         next_outspsr = {op0[31:29], spsr[28:0]};
154                                 else
155                                         next_outcpsr = {op0[31:29], cpsr[28:0]};
156                         end else begin
157                                 if (insn[22] /* Ps */)
158                                         next_outspsr = op0;
159                                 else
160                                         next_outcpsr = op0;
161                         end
162                         next_outcpsrup = 1;
163                 end
164                 `DECODE_ALU_SWP,        /* Atomic swap */
165                 `DECODE_ALU_BX,         /* Branch */
166                 `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
167                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
168                 begin end
169                 `DECODE_ALU:            /* ALU */
170                 begin
171                         alu_in0 = op0;
172                         alu_in1 = op1;
173                         alu_op = insn[24:21];
174                         alu_setflags = insn[20] /* S */;
175                         
176                         if (alu_setres) begin
177                                 next_write_reg = 1;
178                                 next_write_num = insn[15:12] /* Rd */;
179                                 next_write_data = alu_result;
180                         end
181                         
182                         next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
183                         next_outcpsrup = insn[20] /* S */;
184                 end
185                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
186                 `DECODE_LDRSTR,         /* Single data transfer */
187                 `DECODE_LDMSTM:         /* Block data transfer */
188                 begin end
189                 `DECODE_BRANCH:
190                 begin
191                         if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
192                                 jmppc = pc + op0 + 32'h8;
193                                 if(insn[24]) begin
194                                         next_write_reg = 1;
195                                         next_write_num = 4'hE; /* link register */
196                                         next_write_data = pc + 32'h4;
197                                 end
198                                 jmp = 1'b1;
199                         end
200                 end                     /* Branch */
201                 `DECODE_LDCSTC,         /* Coprocessor data transfer */
202                 `DECODE_CDP,            /* Coprocessor data op */
203                 `DECODE_MRCMCR,         /* Coprocessor register transfer */
204                 `DECODE_SWI:            /* SWI */
205                 begin end
206                 default:                /* X everything else out */
207                 begin end
208                 endcase
209         end
210 endmodule
211
212 module Multiplier(
213         input clk,
214         input Nrst,     /* XXX not used yet */
215         
216         input start,
217         input [31:0] acc0,
218         input [31:0] in0,
219         input [31:0] in1,
220         
221         output reg done = 0,
222         output reg [31:0] result);
223         
224         reg [31:0] bitfield;
225         reg [31:0] multiplicand;
226         reg [31:0] acc;
227         
228         always @(posedge clk)
229         begin
230                 if (start) begin
231                         bitfield <= in0;
232                         multiplicand <= in1;
233                         acc <= acc0;
234                         done <= 0;
235                 end else begin
236                         bitfield <= {2'b00, bitfield[31:2]};
237                         multiplicand <= {multiplicand[29:0], 2'b00};
238                         acc <= acc +
239                                 (bitfield[0] ? multiplicand : 0) +
240                                 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
241                         if (bitfield == 0) begin
242                                 result <= acc;
243                                 done <= 1;
244                         end
245                 end
246         end
247 endmodule
248
249 module ALU(
250         input clk,
251         input Nrst,     /* XXX not used yet */
252
253         input [31:0] in0,
254         input [31:0] in1,
255         input [31:0] cpsr,
256         input [3:0] op,
257         input setflags,
258         input shifter_carry,
259
260         output reg [31:0] result,
261         output reg [31:0] cpsr_out,
262         output reg setres
263 );
264         reg [31:0] res;
265         reg flag_n, flag_z, flag_c, flag_v;
266         wire [32:0] sum, diff, rdiff;
267         wire sum_v, diff_v, rdiff_v;
268
269         assign sum = {1'b0, in0} + {1'b0, in1};
270         assign diff = {1'b0, in0} - {1'b0, in1};
271         assign rdiff = {1'b0, in1} - {1'b0, in0};
272         assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
273         assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
274         assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
275
276         always @(*) begin
277                 res = 32'hxxxxxxxx;
278                 setres = 1'bx;
279                 flag_c = cpsr[`CPSR_C];
280                 flag_v = cpsr[`CPSR_V];
281                 case(op)
282                 `ALU_AND: begin
283                         result = in0 & in1;
284                         flag_c = shifter_carry;
285                         setres = 1'b1;
286                 end
287                 `ALU_EOR: begin
288                         result = in0 ^ in1;
289                         flag_c = shifter_carry;
290                         setres = 1'b1;
291                 end
292                 `ALU_SUB: begin
293                         {flag_c, result} = diff;
294                         flag_c = !flag_c;
295                         flag_v = diff_v;
296                         setres = 1'b1;
297                 end
298                 `ALU_RSB: begin
299                         {flag_c, result} = rdiff;
300                         flag_c = !flag_c;
301                         flag_v = rdiff_v;
302                         setres = 1'b1;
303                 end
304                 `ALU_ADD: begin
305                         {flag_c, result} = sum;
306                         flag_v = sum_v;
307                         setres = 1'b1;
308                 end
309                 `ALU_ADC: begin
310                         {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
311                         flag_v = sum_v | (~sum[31] & result[31]);
312                         setres = 1'b1;
313                 end
314                 `ALU_SBC: begin
315                         {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
316                         flag_c = !flag_c;
317                         flag_v = diff_v | (diff[31] & ~result[31]);
318                         setres = 1'b1;
319                 end
320                 `ALU_RSC: begin
321                         {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
322                         flag_c = !flag_c;
323                         flag_v = rdiff_v | (rdiff[31] & ~result[31]);
324                         setres = 1'b1;
325                 end
326                 `ALU_TST: begin
327                         result = in0 & in1;
328                         flag_c = shifter_carry;
329                         setres = 1'b0;
330                 end
331                 `ALU_TEQ: begin
332                         result = in0 ^ in1;
333                         flag_c = shifter_carry;
334                         setres = 1'b0;
335                 end
336                 `ALU_CMP: begin
337                         {flag_c, result} = diff;
338                         flag_c = !flag_c;
339                         flag_v = diff_v;
340                         setres = 1'b0;
341                 end
342                 `ALU_CMN: begin
343                         {flag_c, result} = sum;
344                         flag_v = sum_v;
345                         setres = 1'b0;
346                 end
347                 `ALU_ORR: begin
348                         result = in0 | in1;
349                         flag_c = shifter_carry;
350                         setres = 1'b1;
351                 end
352                 `ALU_MOV: begin
353                         result = in1;
354                         flag_c = shifter_carry;
355                         setres = 1'b1;
356                 end
357                 `ALU_BIC: begin
358                         result = in0 & (~in1);
359                         flag_c = shifter_carry;
360                         setres = 1'b1;
361                 end
362                 `ALU_MVN: begin
363                         result = ~in1;
364                         flag_c = shifter_carry;
365                         setres = 1'b1;
366                 end
367                 endcase
368                 
369                 flag_z = (result == 0);
370                 flag_n = result[31];
371                 
372                 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
373         end
374 endmodule
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